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2020 – today
- 2024
[c52]Bing-Xun Song
, Ting Xin Lin, Yih-Lang Li:
Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources. ISPD 2024: 185-193- 2023
- [j22]Sheng-Hsien Cheng, Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Tsì-Uí Ik, Yih-Lang Li:
Periodic Physical Activity Information Segmentation, Counting and Recognition From Video. IEEE Access 11: 23019-23031 (2023) - [j21]Muhammad Atif Sarwar, Yu-Chen Lin, Yousef-Awwad Daraghmi, Tsì-Uí Ik, Yih-Lang Li:
Skeleton Based Keyframe Detection Framework for Sports Action Analysis: Badminton Smash Case. IEEE Access 11: 90891-90900 (2023) - 2022
- [j20]Tzu-Wei Yu, Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Sheng-Hsien Cheng, Tsì-Uí Ik, Yih-Lang Li:
Spatiotemporal Activity Semantics Understanding Based on Foreground Object Segmentation: iCounter Scenario. IEEE Access 10: 57748-57758 (2022) - [j19]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5568-5581 (2022) - [c51]Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao:
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. ISPD 2022: 107-115 - [c50]Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan:
Challenges and Approaches in VLSI Routing. ISPD 2022: 185-192 - [c49]Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang:
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. ISQED 2022: 1-6 - 2021
- [j18]Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera:
Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. 14: 24-26 (2021) - [c48]Shih-Ting Lin, Hung-Hsiao Wang, Chia-Yu Kuo, Yolo Chen, Yih-Lang Li:
A Complete PCB Routing Methodology with Concurrent Hierarchical Routing. DAC 2021: 1141-1146 - [c47]Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo:
DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. ICCAD 2021: 1-6 - 2020
- [c46]Hong-Chuan Chi, Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Kuan-Wen Liu, Tsì-Uí Ik, Yih-Lang Li:
Smart Self-Checkout Carts Based on Deep Learning for Shopping Activity Recognition. APNOMS 2020: 185-190 - [c45]Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo:
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. ICCAD 2020: 71:1-71:6 - [c44]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera:
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. ICCAD 2020: 157:1-157:8 - [c43]Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li:
/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. ICCAD 2020: 159:1-159:8 - [c42]Muhammad Atif Sarwar, Yousef-Awwad Daraghmi, Kuan-Wen Liu, Hong-Chuan Chi, Tsì-Uí Ik, Yih-Lang Li:
Smart Shopping Carts Based on Mobile Computing and Deep Learning Cloud Services. WCNC 2020: 1-6
2010 – 2019
- 2019
- [j17]Tai-Cheng Lee, Yih-Lang Li:
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2434-2446 (2019) - [c41]Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera:
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. DAC 2019: 120 - [c40]Jianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo:
DATC RDF-2019: Towards a Complete Academic Reference Design Flow. ICCAD 2019: 1-6 - 2018
- [j16]Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin:
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. ACM Trans. Design Autom. Electr. Syst. 23(4): 45:1-45:26 (2018) - [j15]Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Shu-Fei Tsai, Yiyu Shi:
Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 912-923 (2018) - [c39]Ying-Chi Wei, Radhamanjari Samanta, Yih-Lang Li:
LESAR: A dynamic line-end spacing aware detailed router. DATE 2018: 1473-1476 - [c38]Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam:
DATC RDF: an academic flow from logic synthesis to detailed routing. ICCAD 2018: 37 - [c37]Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li:
Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. ISQED 2018: 425-431 - [c36]Yan-Shiun Wu, Hong-Yan Su, Yi-Hsiang Chang, Rasit Onur Topaloglu, Yih-Lang Li:
MapReduce-based pattern classification for design space analysis. VLSI-DAT 2018: 1-4 - [i2]Jinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam:
DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing. CoRR abs/1810.01078 (2018) - 2017
- [c35]Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin:
A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. ACM Great Lakes Symposium on VLSI 2017: 399-402 - [c34]Jinwook Jung, Pei-Yu Lee, Yan-Shiun Wu, Nima Karimpour Darav, Iris Hui-Ru Jiang, Victor N. Kravets, Laleh Behjat, Yih-Lang Li, Gi-Joon Nam:
DATC RDF: Robust design flow database: Invited paper. ICCAD 2017: 872-873 - [c33]Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto:
Near-future traffic evaluation based navigation for automated driving vehicles. Intelligent Vehicles Symposium 2017: 1465-1470 - [c32]Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera:
Pin accessibility evaluating model for improving routability of VLSI designs. SoCC 2017: 56-61 - 2016
- [c31]Kuen-Wey Lin, Yih-Lang Li, Rung-Bin Lin:
Multiple-patterning lithography-aware routing for standard cell layout synthesis. APCCAS 2016: 534-537 - [c30]Jinwook Jung, Iris Hui-Ru Jiang, Gi-Joon Nam, Victor N. Kravets, Laleh Behjat, Yih-Lang Li:
OpenDesign flow database: the infrastructure for VLSI design and design automation research. ICCAD 2016: 42 - 2015
- [j14]Hong-Yan Su, Chieh-Chu Chen, Yih-Lang Li, An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang:
A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 95-108 (2015) - [c29]Hong-Yan Su, Chih-Hao Hsu, Yih-Lang Li:
SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding. DATE 2015: 1583-1586 - 2014
- [j13]Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li:
Minimizing Critical Area on Gridless Wire Ordering, Sizing and Spacing. J. Inf. Sci. Eng. 30(1): 157-177 (2014) - [j12]Wen-Hao Liu, Yih-Lang Li:
Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 613-626 (2014) - [c28]Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang:
Density-aware Detailed Placement with Instant Legalization. DAC 2014: 122:1-122:6 - [c27]Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Yiyu Shi, Shu-Fei Tsai:
Fast and accurate emissivity and absolute temperature maps measurement for integrated circuits. ICCAD 2014: 542-549 - [c26]Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li:
Skillfully diminishing antenna effect in layer assignment stage. VLSI-DAT 2014: 1-4 - [i1]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: a triple patterning lithography aware detailed router. CoRR abs/1402.2906 (2014) - 2013
- [j11]Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 709-722 (2013) - [c25]Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan:
Routing congestion estimation with real design constraints. DAC 2013: 92:1-92:8 - [c24]Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Optimization of placement solutions for routability. DAC 2013: 153:1-153:9 - [c23]Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. ISPD 2013: 114-119 - 2012
- [j10]Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 459-472 (2012) - [c22]Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li:
Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. ASP-DAC 2012: 437-442 - [c21]Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li:
TRIAD: A triple patterning lithography aware detailed router. ICCAD 2012: 123-129 - [c20]Iris Hui-Ru Jiang, Zhuo Li, Yih-Lang Li:
Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. ICCAD 2012: 341 - [c19]Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh:
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. ICCAD 2012: 713-719 - [c18]Wen-Hao Liu, Yih-Lang Li:
Optimizing the antenna area and separators in layer assignment of multi-layer global routing. ISPD 2012: 137-144 - 2011
- [j9]Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li:
Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1335-1348 (2011) - [j8]Yih-Lang Li, Yu-Ning Chang, Wen-Nai Cheng:
A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment. ACM Trans. Design Autom. Electr. Syst. 16(2): 19:1-19:25 (2011) - [c17]Wen-Hao Liu, Yih-Lang Li:
Negotiation-based layer assignment for via count and via overflow minimization. ASP-DAC 2011: 539-544 - [c16]Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao:
High-quality global routing for multiple dynamic supply voltage designs. ICCAD 2011: 263-269 - [c15]Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li:
Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. ICCAD 2011: 283-289 - [c14]Yu-Wei Lee, Yen-Hung Lin, Yih-Lang Li:
Gridless wire ordering, sizing and spacing with critical area minimization. ISQED 2011: 646-653 - 2010
- [c13]Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen:
Minimizing clock latency range in robust clock tree synthesis. ASP-DAC 2010: 389-394 - [c12]Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li:
Dead via minimization by simultaneous routing and redundant via insertion. ASP-DAC 2010: 657-662 - [c11]Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao:
Multi-threaded collision-aware global routing with bounded-length maze routing. DAC 2010: 200-205 - [c10]Yen-Hung Lin, Yih-Lang Li:
Double patterning lithography aware gridless detailed routing with innovative conflict graph. DAC 2010: 398-403
2000 – 2009
- 2009
- [j7]Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li:
Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(3): 880-889 (2009) - [c9]Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. ASP-DAC 2009: 570-575 - [c8]Ke-Ren Dai, Chien-Hung Lu, Yih-Lang Li:
GRPlacer: Improving routability and wire-length of global routing with circuit replacement. ICCAD 2009: 351-356 - [c7]De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li:
Topology-driven cell layout migration with collinear constraints. ICCD 2009: 439-444 - [c6]Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li:
Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. ISPD 2009: 151-158 - 2008
- [j6]Yiming Li, Shao-Ming Yu, Yih-Lang Li:
Parallel solution of large-scale eigenvalue problem for master equation in protein folding dynamics. J. Parallel Distributed Comput. 68(5): 678-685 (2008) - [j5]Yiming Li, Shao-Ming Yu, Yih-Lang Li:
Electronic design automation using a unified optimization framework. Math. Comput. Simul. 79(4): 1137-1152 (2008) - [j4]Yiming Li, Yih-Lang Li, Shao-Ming Yu:
Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique. Math. Comput. Simul. 79(4): 1165-1177 (2008) - [c5]Yu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng:
Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. ISPD 2008: 134-141 - [c4]Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li:
Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. ISQED 2008: 514-519 - 2007
- [j3]Yih-Lang Li, Jin-Yih Li, Wen-Bin Chen:
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 345-358 (2007) - [j2]Yih-Lang Li, Hsin-Yu Chen, Chih-Ta Lin:
NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 705-718 (2007) - [c3]Yiming Li, Shao-Ming Yu, Yih-Lang Li:
A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation. International Conference on Computational Science (4) 2007: 259-266 - 2005
- [c2]Jin-Yih Li, Yih-Lang Li:
An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow. ISPD 2005: 7-13
1990 – 1999
- 1995
- [j1]Yih-Lang Li, Cheng-Wen Wu:
Cellular automata for efficient parallel logic and fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 740-749 (1995) - 1994
- [c1]Yih-Lang Li, Cheng-Wen Wu:
Logic and Fault Simulation by Cellular Automata. EDAC-ETC-EUROASIC 1994: 552-556
Coauthor Index
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