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ORCIDUri C. Weiser
Person information
- affiliation: Technion - Israel Institute of Technology, Haifa, Israel
- award (2016): Eckert-Mauchly Award
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2020 – today
- 2023
[j27]Samer Kurzum
, Gil Shomron, Freddy Gabbay, Uri C. Weiser:
Enhancing DNN Training Efficiency Via Dynamic Asymmetric Architecture. IEEE Comput. Archit. Lett. 22(1): 49-52 (2023)- 2021
- [c17]Gil Shomron, Freddy Gabbay, Samer Kurzum, Uri C. Weiser:
Post-Training Sparsity-Aware Quantization. NeurIPS 2021: 17737-17748 - [i12]Gil Shomron, Freddy Gabbay, Samer Kurzum, Uri C. Weiser:
Post-Training Sparsity-Aware Quantization. CoRR abs/2105.11010 (2021) - 2020
- [j26]Leeor Peled, Uri C. Weiser, Yoav Etsion:
A Neural Network Prefetcher for Arbitrary Memory Access Patterns. ACM Trans. Archit. Code Optim. 16(4): 37:1-37:27 (2020) - [c16]Gil Shomron, Ron Banner, Moran Shkolnik, Uri C. Weiser:
Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. ECCV (10) 2020: 234-250 - [c15]Gil Shomron, Uri C. Weiser:
Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. MICRO 2020: 256-269 - [c14]Moran Shkolnik, Brian Chmiel, Ron Banner, Gil Shomron, Yury Nahshan, Alex M. Bronstein, Uri C. Weiser:
Robust Quantization: One Model to Rule Them All. NeurIPS 2020 - [i11]Moran Shkolnik, Brian Chmiel, Ron Banner, Gil Shomron, Yury Nahshan, Alexander M. Bronstein, Uri C. Weiser:
Robust Quantization: One Model to Rule Them All. CoRR abs/2002.07686 (2020) - [i10]Gil Shomron, Uri C. Weiser:
Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks. CoRR abs/2004.09309 (2020) - [i9]Leeor Peled, Uri C. Weiser, Yoav Etsion:
Semantic prefetching using forecast slices. CoRR abs/2005.06102 (2020) - [i8]Gil Shomron, Uri C. Weiser:
Post-Training BatchNorm Recalibration. CoRR abs/2010.05625 (2020)
2010 – 2019
- 2019
- [j25]Gil Shomron, Uri C. Weiser:
Spatial Correlation and Value Prediction in Convolutional Neural Networks. IEEE Comput. Archit. Lett. 18(1): 10-13 (2019) - [j24]Gil Shomron, Tal Horowitz, Uri C. Weiser:
SMT-SA: Simultaneous Multithreading in Systolic Arrays. IEEE Comput. Archit. Lett. 18(2): 99-102 (2019) - [i7]Gil Shomron, Ron Banner, Moran Shkolnik, Uri C. Weiser:
Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks. CoRR abs/1909.07636 (2019) - 2018
- [i6]Leeor Peled, Uri C. Weiser, Yoav Etsion:
Towards Memory Prefetching with Neural Networks: Challenges and Insights. CoRR abs/1804.00478 (2018) - [i5]Gil Shomron, Uri C. Weiser:
Exploiting Spatial Correlation in Convolutional Neural Networks for Activation Value Prediction. CoRR abs/1807.10598 (2018) - 2017
- [j23]Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser:
Optimizing Read-Once Data Flow in Big-Data Applications. IEEE Comput. Archit. Lett. 16(1): 68-71 (2017) - [j22]Leonid Yavits, Uri C. Weiser, Ran Ginosar:
Resistive Address Decoder. IEEE Comput. Archit. Lett. 16(2): 141-144 (2017) - [j21]Uri C. Weiser:
Insights from the 2016 Eckert-Mauchly Award Recipient. IEEE Micro 37(3): 126-128 (2017) - [j20]Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. IEEE Micro 37(4): 20-28 (2017) - [i4]Roman Kaplan, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment. CoRR abs/1701.04723 (2017) - [i3]Leonid Yavits, Amir Morad, Uri C. Weiser, Ran Ginosar:
MultiAmdahl: Optimal Resource Allocation in Heterogeneous Architectures. CoRR abs/1705.06923 (2017) - 2016
- [j19]Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ran Ginosar, Eliezer Weissmann, Yoni Aizik:
H-EARtH: Heterogeneous Multicore Platform Energy Management. Computer 49(10): 47-55 (2016) - [j18]Tomer Y. Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems. J. Parallel Distributed Comput. 95: 3-14 (2016) - [c13]Uri C. Weiser:
Potential future research in computing: Heterogeneous systems, memory subsystems - Process-in-storage, or not to process-in-storage? That is the question. SAMOS 2016: i - [i2]Leonid Yavits, Amir Morad, Ran Ginosar, Uri C. Weiser:
Convex Optimization of Real Time SoC. CoRR abs/1601.07815 (2016) - 2015
- [j17]Leonid Azriel, Avi Mendelson, Uri C. Weiser:
Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck. IEEE Comput. Archit. Lett. 14(1): 54-57 (2015) - [j16]Efraim Rotem, Ran Ginosar, Avi Mendelson, Uri C. Weiser:
Power and thermal constraints of modern system-on-a-chip computer. Microelectron. J. 46(12): 1225-1229 (2015) - [c12]Leeor Peled, Shie Mannor, Uri C. Weiser, Yoav Etsion:
Semantic locality and context-based prefetching using reinforcement learning. ISCA 2015: 285-297 - 2014
- [j15]Efraim Rotem, Ran Ginosar, Uri C. Weiser, Avi Mendelson:
Energy Aware Race to Halt: A Down to EARtH Approach for Platform Energy Management. IEEE Comput. Archit. Lett. 13(1): 25-28 (2014) - [j14]Amir Morad, Tomer Y. Morad, Leonid Yavits, Ran Ginosar, Uri C. Weiser:
Generalized MultiAmdahl: Optimization of Heterogeneous Multi-Accelerator SoC. IEEE Comput. Archit. Lett. 13(1): 37-40 (2014) - [j13]Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Multithreading. IEEE Comput. Archit. Lett. 13(1): 41-44 (2014) - [j12]Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 895-899 (2014) - [j11]Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2054-2066 (2014) - [c11]Adi Fuchs, Shie Mannor, Uri C. Weiser, Yoav Etsion:
Loop-Aware Memory Prefetching Using Code Block Working Sets. MICRO 2014: 533-544 - [c10]Efraim Rotem, Uri C. Weiser, Avi Mendelson, Ahmad Yasin, Ran Ginosar:
Energy management of highly dynamic server workloads in an heterogeneous data center. PATMOS 2014: 1-5 - 2013
- [j10]Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser:
Optimal Resource Allocation with MultiAmdahl. Computer 46(7): 70-77 (2013) - [j9]Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 211-221 (2013) - 2012
- [j8]Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser:
MultiAmdahl: How Should I Divide My Heterogenous Chip? IEEE Comput. Archit. Lett. 11(2): 65-68 (2012) - [j7]Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser:
Task Scheduling Based On Thread Essence and Resource Limitations. J. Comput. 7(1): 53-64 (2012) - 2011
- [c9]Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman:
Memristor-based IMPLY logic design procedure. ICCD 2011: 142-147 - [i1]Tsahee Zidenberg, Isaac Keslassy, Uri C. Weiser:
Multi-Amdahl: Optimal Resource Sharing with Multiple Program Execution Segments. CoRR abs/1105.2960 (2011) - 2010
- [c8]Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Threads vs. caches: Modeling the behavior of parallel workloads. ICCD 2010: 274-281 - [c7]Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser:
Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors. PAAP 2010: 65-72 - [e1]André Seznec, Uri C. Weiser, Ronny Ronen:
37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM 2010, ISBN 978-1-4503-0053-7 [contents]
2000 – 2009
- 2009
- [j6]Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Many-Core vs. Many-Thread Machines: Stay Away From the Valley. IEEE Comput. Archit. Lett. 8(1): 25-28 (2009) - [c6]Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser:
Multiple clock and voltage domains for chip multi processors. MICRO 2009: 459-468 - 2008
- [j5]A. Elyada, Ran Ginosar, Uri C. Weiser:
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1243-1248 (2008) - [c5]Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
Utilizing shared data in chip multiprocessors with the nahalal architecture. SPAA 2008: 1-10 - 2007
- [j4]Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
Nahalal: Cache Organization for Chip Multiprocessors. IEEE Comput. Archit. Lett. 6(1): 21-24 (2007) - 2006
- [j3]Tomer Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Valero, Eduard Ayguadé:
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. IEEE Comput. Archit. Lett. 5(1): 14-17 (2006) - 2004
- [c4]Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir:
Interconnect-power dissipation in a microprocessor. SLIP 2004: 7-13
1990 – 1999
- 1999
- [c3]Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser:
Correlated Load-Address Predictors. ISCA 1999: 54-63 - 1997
- [j2]Alex Peleg, Sam Wilkie, Uri C. Weiser:
Intel MMX for Multimedia PCs. Commun. ACM 40(1): 24-38 (1997) - [c2]Oded Lempel, Alex Peleg, Uri C. Weiser:
Intel's MMX™ technology-a new instruction set extension. COMPCON 1997: 255-259 - 1996
- [j1]Alex Peleg, Uri C. Weiser:
MMX technology extension to the Intel architecture. IEEE Micro 16(4): 42-50 (1996) - 1991
- [c1]Fabian Klass, Uri C. Weiser:
Efficient Systolic Array for Matrix Multiplication. ICPP (3) 1991: 21-25
Coauthor Index
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