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2020 – today
- 2024
[j128]Alexander J. Edwards
, Gleb Krylov, Joseph S. Friedman, Eby G. Friedman:
Harnessing stochasticity for superconductive multi-layer spike-rate-coded neuromorphic networks. Neuromorph. Comput. Eng. 4(1): 14005 (2024)- [j127]Rassul Bairamkulov, Eby G. Friedman:
Power Aware Placement of On-Chip Voltage Regulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 654-666 (2024) - [j126]Guangchao Zhao, Zhiwei Zeng, Xingli Wang, Abdelrahman G. Qoutb, Philippe Coquet, Eby G. Friedman, Beng Kang Tay, Mingqiang Huang:
Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms. IEEE Trans. Emerg. Top. Comput. 12(3): 826-839 (2024) - [j125]Ana Mitrovic, Eby G. Friedman:
Thermal Exploration of RSFQ Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 728-738 (2024) - 2023
- [j124]Andres Ayes, Eby G. Friedman:
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces. Integr. 93: 102066 (2023) - [j123]Abdelrahman G. Qoutb, Eby G. Friedman:
Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing. Microelectron. J. 131: 105635 (2023) - [j122]Nurzhan Zhuldassov, Eby G. Friedman:
Temperature-frequency boundary of cryogenic dynamic logic. Microelectron. J. 135: 105763 (2023) - [j121]Nurzhan Zhuldassov, Rassul Bairamkulov, Eby G. Friedman:
Thermal Optimization of Hybrid Cryogenic Computing Systems. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1339-1346 (2023) - [c184]Andres Ayes, Eby G. Friedman:
Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks. SOCC 2023: 1-5 - [i1]Gleb Krylov, Alexander J. Edwards, Joseph S. Friedman, Eby G. Friedman:
Deep Neuromorphic Networks with Superconducting Single Flux Quanta. CoRR abs/2311.10721 (2023) - 2022
- [j120]Gleb Krylov, Eby G. Friedman:
Inductive noise coupling in multilayer superconductive ICs. Microelectron. J. 126: 105336 (2022) - [j119]Rassul Bairamkulov, Abinash Roy, Mahalingam Nagarajan, Vaishnav Srinivas, Eby G. Friedman:
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2263-2275 (2022) - [j118]Rassul Bairamkulov, Tahereh Jabbari, Eby G. Friedman:
QuCTS - Single-Flux Quantum Clock Tree Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3346-3358 (2022) - [j117]Issa Salameh, Eby G. Friedman, Shahar Kvatinsky:
Superconductive Logic Using 2ϕ - Josephson Junctions With Half Flux Quantum Pulses. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2533-2537 (2022) - [j116]Tahereh Jabbari, Eby G. Friedman:
Surface Inductance of Superconductive Striplines. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2952-2956 (2022) - [c183]Abdelrahman G. Qoutb, Eby G. Friedman:
Double Magnetic Tunnel Junction-Based Nonvolatile Logic. ISCAS 2022: 311-315 - [c182]Nurzhan Zhuldassov, Kan Xu, Eby G. Friedman:
Converter Topologies for On-Package Voltage Stacking. ISCAS 2022: 546-550 - 2021
- [c181]Rassul Bairamkulov, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas, Eby G. Friedman:
SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping. DAC 2021: 283-288 - [c180]Ana Mitrovic, Eby G. Friedman:
MTJ-Based Dithering for Stochastic Analog-to-Digital Conversion. ISCAS 2021: 1-5 - [c179]Gleb Krylov, Eby G. Friedman:
Inductive Noise Coupling in Superconductive Passive Transmission Lines. MWSCAS 2021: 727-731 - 2020
- [j115]Rassul Bairamkulov, Kan Xu, Mikhail Popovich, Juan Ochoa, Vaishnav Srinivas, Eby G. Friedman:
Power Delivery Exploration Methodology Based on Constrained Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1916-1924 (2020) - [j114]Rassul Bairamkulov, Eby G. Friedman:
Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 3224-3233 (2020) - [j113]Albert Ciprut, Eby G. Friedman:
Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 414-420 (2020) - [j112]Abdelrahman G. Qoutb, Eby G. Friedman:
Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1505-1512 (2020) - [j111]Gleb Krylov, Eby G. Friedman:
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2438-2447 (2020) - [c178]Rassul Bairamkulov, Eby G. Friedman, Abinash Roy, Mali Nagarajan, Vaishnav Srinivas:
Graph-Based Power Network Routing for Board-Level High Performance Systems. ISCAS 2020: 1-5 - [c177]Gleb Krylov, Eby G. Friedman:
Bias Distribution in ERSFQ VLSI Circuits. ISCAS 2020: 1-5 - [c176]Abdelrahman G. Qoutb, Eby G. Friedman:
Spintronic/CMOS-Based Thermal Sensors. ISCAS 2020: 1-5 - [c175]Boris Vaisband, Ange Maurice, Chong Wei Tan, Beng Kang Tay, Eby G. Friedman:
Multi-Bit CNT TSV for 3-D ICs. ISCAS 2020: 1-5 - [c174]Kan Xu, Eby G. Friedman:
Challenges in High Current On-Chip Voltage Stacked Systems. ISCAS 2020: 1-5 - [c173]Kan Xu, Eby G. Friedman, Mikhail Popovich, Gregory Sizikov:
Distributed Port Assignment for Extraction of Power Delivery Networks. ISCAS 2020: 1-5 - [c172]Nurzhan Zhuldassov, Eby G. Friedman:
Cryogenic Dynamic Logic. ISCAS 2020: 1-5 - [c171]Tahereh Jabbari, Eby G. Friedman:
Global interconnects in VLSI complexity single flux quantum systems. SLIP 2020: 4
2010 – 2019
- 2019
- [j110]Rassul Bairamkulov, Eby G. Friedman:
Effective Resistance of Two-Dimensional Truncated Infinite Mesh Structures. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4368-4376 (2019) - [j109]Albert Ciprut, Eby G. Friedman:
Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators. IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1779-1789 (2019) - [c170]Abdelrahman G. Qoutb, Eby G. Friedman:
PMTJ Temperature Sensor Utilizing VCMA. ISCAS 2019: 1-5 - 2018
- [j108]Boris Vaisband, Eby G. Friedman:
Heterogeneous 3-D ICs as a platform for hybrid energy harvesting in IoT systems. Future Gener. Comput. Syst. 87: 152-158 (2018) - [j107]Kan Xu, Ravi Patel, Praveen Raghavan, Eby G. Friedman:
Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs. Integr. 61: 11-19 (2018) - [j106]Yang Zhang, Xiaoping Wang, Eby G. Friedman:
Memristor-Based Circuit Design for Multilayer Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 677-686 (2018) - [j105]Albert Ciprut, Eby G. Friedman:
Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 711-719 (2018) - [c169]Abdelrahman G. Qoutb, Eby G. Friedman:
MTJ Magnetization Switching Mechanisms for IoT Applications. ACM Great Lakes Symposium on VLSI 2018: 347-352 - [c168]Rassul Bairamkulov, Kan Xu, Eby G. Friedman, Mikhail Popovich, Juan Ochoa, Vaishnav Srinivas:
Versatile Framework for Power Delivery Exploration. ISCAS 2018: 1-5 - [c167]Albert Ciprut, Eby G. Friedman:
Hybrid Write Bias Scheme for Non-Volatile Resistive Crossbar Arrays. ISCAS 2018: 1-5 - [c166]Gleb Krylov, Eby G. Friedman:
Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor. ISCAS 2018: 1-5 - [c165]Albert Ciprut, Eby G. Friedman:
On the write energy of non-volatile resistive crossbar arrays with selectors. ISQED 2018: 184-188 - 2017
- [j104]Alexander E. Shapiro, Eby G. Friedman:
Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies. J. Low Power Electron. 13(3): 395-401 (2017) - [j103]Boris Vaisband, Eby G. Friedman:
Hexagonal TSV Bundle Topology for 3-D ICs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 11-15 (2017) - [j102]Yang Zhang, Xiaoping Wang, Yi Li, Eby G. Friedman:
Memristive Model for Synaptic Circuits. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 767-771 (2017) - [j101]Albert Ciprut, Eby G. Friedman:
Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 286-293 (2017) - [c164]Gleb Krylov, Eby G. Friedman:
Test point insertion for RSFQ circuits. ISCAS 2017: 1-4 - [c163]Boris Vaisband, Eby G. Friedman:
Hybrid energy harvesting in 3-D IC IoT devices. ISCAS 2017: 1-4 - [c162]Albert Ciprut, Eby G. Friedman:
On the stability of distributed on-chip low dropout regulators. MWSCAS 2017: 217-220 - 2016
- [j100]Alexander E. Shapiro, Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, Eby G. Friedman:
Adaptive power gating of 32-bit Kogge Stone adder. Integr. 53: 80-87 (2016) - [j99]Ioannis Savidis, Berkehan Ciftcioglu, Jie Xu, Jianyun Hu, Manish Jain, Rebecca Berman, Jing Xue, Peng Liu, Duncan Moore, Gary Wicks, Michael C. Huang, Hui Wu, Eby G. Friedman:
Heterogeneous 3-D circuits: Integrating free-space optics with CMOS. Microelectron. J. 50: 66-75 (2016) - [j98]Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eby G. Friedman:
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 129-138 (2016) - [j97]Jinhui Wang, Na Gong, Eby G. Friedman:
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 613-624 (2016) - [j96]Alexander E. Shapiro, Eby G. Friedman:
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 774-778 (2016) - [j95]Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Eby G. Friedman, Engin Ipek:
Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1266-1279 (2016) - [j94]Boris Vaisband, Eby G. Friedman:
Noise Coupling Models in Heterogeneous 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2778-2786 (2016) - [c161]Ravi Patel, Kan Xu, Eby G. Friedman, Praveen Raghavan:
Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs. ACM Great Lakes Symposium on VLSI 2016: 233-238 - [c160]Ravi Patel, Eby G. Friedman, Praveen Raghavan:
Power noise in 14, 10, and 7 nm FinFET CMOS technologies. ISCAS 2016: 37-40 - [c159]Albert Ciprut, Eby G. Friedman:
Design models of resistive crossbar arrays with selector devices. ISCAS 2016: 1250-1253 - [c158]Boris Vaisband, Eby G. Friedman:
Layer ordering to minimize TSVs in heterogeneous 3-D ICs. ISCAS 2016: 1926-1929 - 2015
- [j93]Inna Vaisband, Eby G. Friedman:
Energy efficient adaptive clustering of on-chip power delivery systems. Integr. 48: 1-9 (2015) - [j92]Kan Xu, Eby G. Friedman:
Scaling trends of power noise in 3-D ICs. Integr. 51: 139-148 (2015) - [j91]Qing Guo, Xiaochen Guo, Yuxin Bai, Ravi Patel, Engin Ipek, Eby G. Friedman:
Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing. IEEE Micro 35(5): 62-71 (2015) - [j90]Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny:
VTEAM: A General Model for Voltage-Controlled Memristors. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 786-790 (2015) - [j89]Mohammad Kazemi, Engin Ipek, Eby G. Friedman:
Energy-Efficient Nonvolatile Flip-Flop With Subnanosecond Data Backup Time for Fine-Grain Power Gating. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1154-1158 (2015) - [j88]Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny:
Multistate Register Based on Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1750-1759 (2015) - [j87]Ioannis Savidis, Boris Vaisband, Eby G. Friedman:
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2077-2089 (2015) - [c157]Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Engin Ipek, Eby G. Friedman:
Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime. ICCD 2015: 527-534 - [c156]Boris Vaisband, Eby G. Friedman:
3-D floorplanning algorithm to minimize thermal interactions. ISCAS 2015: 2133-2136 - [c155]Kan Xu, Eby G. Friedman:
Inductive coupling effects in large TSV arrays. ISCAS 2015: 2888-2891 - 2014
- [j86]Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Multithreading. IEEE Comput. Archit. Lett. 13(1): 41-44 (2014) - [j85]Ravi Patel, Engin Ipek, Eby G. Friedman:
2T-1R STT-MRAM memory cells for enhanced on/off current ratio. Microelectron. J. 45(2): 133-143 (2014) - [j84]Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky:
Logic operations in memory using a memristive Akers array. Microelectron. J. 45(11): 1429-1437 (2014) - [j83]Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 895-899 (2014) - [j82]Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2054-2066 (2014) - [j81]Inna Vaisband, Mahmood J. Azhar, Eby G. Friedman, Selçuk Köse:
Digitally Controlled Pulse Width Modulator for On-Chip Power Management. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2527-2534 (2014) - [c154]Boris Vaisband, Ioannis Savidis, Eby G. Friedman:
Thermal conduction path analysis in 3-D ICs. ISCAS 2014: 594-597 - [c153]Inna Vaisband, Eby G. Friedman:
Computationally efficient clustering of power supplies in heterogeneous real time systems. ISCAS 2014: 1628-1631 - [c152]Ravi Patel, Engin Ipek, Eby G. Friedman:
Field driven STT-MRAM cell for reduced switching latency and energy. ISCAS 2014: 2173-2176 - [c151]Ravi Patel, Eby G. Friedman:
Sub-crosspoint RRAM decoding for improved area efficiency. NANOARCH 2014: 98-103 - [c150]Inna Vaisband, Eby G. Friedman:
Dynamic power management with power network-on-chip. NEWCAS 2014: 225-228 - [c149]Inna Vaisband, Eby G. Friedman:
Power network-on-chip for scalable power delivery. SLIP 2014: 1:1-1:5 - 2013
- [j80]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. Integr. 46(4): 382-391 (2013) - [j79]Ioannis Savidis, Selçuk Köse, Eby G. Friedman:
Power Noise in TSV-Based 3-D Integrated Circuits. IEEE J. Solid State Circuits 48(2): 587-597 (2013) - [j78]Shen Ge, Eby G. Friedman:
Data bus swizzling in TSV-based three-dimensional integrated circuits. Microelectron. J. 44(8): 696-705 (2013) - [j77]Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 211-221 (2013) - [j76]Selçuk Köse, Simon Tam, Sally Pinzon, Bruce McDermott, Eby G. Friedman:
Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 680-691 (2013) - [j75]Renatas Jakushokas, Eby G. Friedman:
Power Network Optimization Based on Link Breaking Methodology. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 983-987 (2013) - [c148]Qing Guo, Xiaochen Guo, Ravi Patel, Engin Ipek, Eby G. Friedman:
AC-DIMM: associative computing with STT-MRAM. ISCA 2013: 189-200 - [c147]Selçuk Köse, Inna Vaisband, Eby G. Friedman:
Digitally controlled wide range pulse width modulator for on-chip power supplies. ISCAS 2013: 2251-2254 - [c146]Selçuk Köse, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Current profile of a microcontroller to determine electromagnetic emissions. ISCAS 2013: 2650-2653 - 2012
- [j74]Selçuk Köse, Eby G. Friedman:
Distributed On-Chip Power Delivery. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(4): 704-713 (2012) - [j73]Selçuk Köse, Eby G. Friedman:
Efficient algorithms for fast IR drop analysis exploiting locality. Integr. 45(2): 149-161 (2012) - [j72]Emre Salman, Eby G. Friedman:
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits. Microelectron. J. 43(2): 119-127 (2012) - [j71]Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny:
Multi-aggressor capacitive and inductive coupling noise modeling and mitigation. Microelectron. J. 43(4): 235-243 (2012) - [c145]Selçuk Köse, Eby G. Friedman:
Distributed power delivery for energy efficient and low power systems. ACSCC 2012: 757-761 - [c144]Renatas Jakushokas, Eby G. Friedman:
Link breaking methodology: mitigating noise within power networks. ACM Great Lakes Symposium on VLSI 2012: 129-134 - [c143]Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Energy metrics for power efficient crosslink and mesh topologies. ISCAS 2012: 1656-1659 - [c142]Selçuk Köse, Eby G. Friedman, Simon Tarn, Sally Pinzon, Bruce McDermott:
An area efficient on-chip hybrid voltage regulator. ISQED 2012: 398-403 - [c141]Ravi Patel, Engin Ipek, Eby G. Friedman:
STT-MRAM memory cells with enhanced on/off ratio. SoCC 2012: 148-152 - [c140]Ravi Patel, Eby G. Friedman:
Arithmetic encoding for memristive multi-bit storage. VLSI-SoC 2012: 99-104 - 2011
- [j70]Jinhui Wang, Ioannis Savidis, Eby G. Friedman:
Thermal analysis of oxide-confined VCSEL arrays. Microelectron. J. 42(5): 820-825 (2011) - [j69]Selçuk Köse, Eby G. Friedman:
Effective Resistance of a Two Layer Mesh. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 739-743 (2011) - [j68]Renatas Jakushokas, Eby G. Friedman:
Multi-Layer Interdigitated Power Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 774-786 (2011) - [j67]Jonathan Rosenfeld, Eby G. Friedman:
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1075-1085 (2011) - [j66]Selçuk Köse, Emre Salman, Eby G. Friedman:
Shielding Methodologies in the Presence of Power/Ground Noise. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1458-1468 (2011) - [j65]Jonathan Rosenfeld, Eby G. Friedman:
Linear and Switch-Mode Conversion in 3-D Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 2095-2108 (2011) - [j64]Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock Distribution Networks in 3-D Integrated Systems. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2256-2266 (2011) - [c139]Selçuk Köse, Eby G. Friedman:
Fast algorithms for IR voltage drop analysis exploiting locality. DAC 2011: 996-1001 - [c138]Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman:
Memristor-based IMPLY logic design procedure. ICCD 2011: 142-147 - [c137]Ioannis Savidis, Vasilis F. Pavlidis, Eby G. Friedman:
Clock distribution models of 3-D integrated systems. ISCAS 2011: 2225-2228 - [c136]Selçuk Köse, Eby G. Friedman:
Distributed power network co-design with on-chip power supplies and decoupling capacitors. SLIP 2011: 1-5 - [p1]Vasilis F. Pavlidis, Eby G. Friedman:
Physical Analysis of NoC Topologies for 3-D Integrated Systems. 3D Integration for NoC-based SoC Architectures 2011: 89-114 - 2010
- [j63]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 689-696 (2010) - [j62]Renatas Jakushokas, Eby G. Friedman:
Resource Based Optimization for Simultaneous Shield and Repeater Insertion. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 742-749 (2010) - [j61]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1262 (2010) - [c135]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20 - [c134]Renatas Jakushokas, Eby G. Friedman:
Line width optimization for interdigitated power/ground networks. ACM Great Lakes Symposium on VLSI 2010: 329-334 - [c133]Selçuk Köse, Eby G. Friedman:
On-chip point-of-load voltage regulator for distributed power supplies. ACM Great Lakes Symposium on VLSI 2010: 377-380 - [c132]Emre Salman, Eby G. Friedman:
Methodology to achieve higher tolerance to delay variations in synchronous circuits. ACM Great Lakes Symposium on VLSI 2010: 447-452 - [c131]Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson:
Efficiency optimization of integrated DC-DC buck converters. ICECS 2010: 1208-1211 - [c130]Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore:
An intra-chip free-space optical interconnect. ISCA 2010: 94-105 - [c129]Renatas Jakushokas, Eby G. Friedman:
Globally integrated power and clock distribution network. ISCAS 2010: 1751-1754 - [c128]Renatas Jakushokas, Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin, Cynthia L. Recker:
Compact substrate models for efficient noise coupling and signal isolation analysis. ISCAS 2010: 2346-2349 - [c127]Selçuk Köse, Eby G. Friedman:
An area efficient fully monolithic hybrid voltage regulator. ISCAS 2010: 2718-2721 - [c126]Renatas Jakushokas, Eby G. Friedman:
Methodology for multi-layer interdigitated power and ground network design. ISCAS 2010: 3208-3211 - [c125]Selçuk Köse, Eby G. Friedman:
Fast algorithms for power grid analysis based on effective resistance. ISCAS 2010: 3661-3664 - [c124]Selçuk Köse, Eby G. Friedman:
Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors. SoCC 2010: 15-18
2000 – 2009
- 2009
- [j60]Guoqing Chen, Eby G. Friedman:
Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction. J. Circuits Syst. Comput. 18(7): 1263-1285 (2009) - [j59]Vasilis F. Pavlidis, Eby G. Friedman:
Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits. Proc. IEEE 97(1): 123-140 (2009) - [j58]Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 997-1004 (2009) - [j57]Renatas Jakushokas, Eby G. Friedman:
Inductance Model of Interdigitated Power and Ground Distribution Networks. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 585-589 (2009) - [j56]Jonathan Rosenfeld, Eby G. Friedman:
Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology. IEEE Trans. Very Large Scale Integr. Syst. 17(2): 181-193 (2009) - [j55]Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1405-1418 (2009) - [j54]Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1559-1564 (2009) - [c123]Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Contact merging algorithm for efficient substrate noise analysis in large scale circuits. ACM Great Lakes Symposium on VLSI 2009: 9-14 - [c122]Renatas Jakushokas, Eby G. Friedman:
Simultaneous shield and repeater insertion. ACM Great Lakes Symposium on VLSI 2009: 15-20 - [c121]Eby G. Friedman:
Design challenges in high performance three-dimensional circuits. ACM Great Lakes Symposium on VLSI 2009: 281-282 - [c120]Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Power efficient tree-based crosslinks for skew reduction. ACM Great Lakes Symposium on VLSI 2009: 285-290 - [c119]Renatas Jakushokas, Eby G. Friedman:
Minimizing Noise Via Shield and Repeater Insertion. ISCAS 2009: 2265-2268 - [c118]Selçuk Köse, Emre Salman, Eby G. Friedman:
Shielding Methodologies in the Presence of Power/Ground Noise. ISCAS 2009: 2277-2280 - [c117]Jonathan Rosenfeld, Eby G. Friedman:
On-chip DC-DC converters for three-dimensional ICs. ISQED 2009: 759-764 - 2008
- [j53]Vasilis F. Pavlidis, Eby G. Friedman:
Timing-driven via placement heuristics for three-dimensional ICs. Integr. 41(4): 489-508 (2008) - [j52]Guoqing Chen, Eby G. Friedman:
Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 26-30 (2008) - [j51]Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman:
Effective Radii of On-Chip Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 894-907 (2008) - [j50]Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny:
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 908-921 (2008) - [j49]Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1717-1721 (2008) - [c116]Vasilis F. Pavlidis, Ioannis Savidis, Eby G. Friedman:
Clock distribution networks for 3-D ictegrated Circuits. CICC 2008: 651-654 - [c115]Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Input port reduction for efficient substrate extraction in large scale IC's. ISCAS 2008: 376-379 - [c114]Ioannis Savidis, Eby G. Friedman:
Electrical modeling and characterization of 3-D vias. ISCAS 2008: 784-787 - [c113]Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Equivalent rise time for resonance in power/ground noise estimation. ISCAS 2008: 2422-2425 - [c112]Guoqing Chen, Eby G. Friedman:
Transient simulation of on-chip transmission lines via exact pole extraction. ISCAS 2008: 2757-2760 - [c111]Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. ISQED 2008: 261-266 - [c110]Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny:
Timing optimization in logic with interconnect. SLIP 2008: 19-26 - [c109]Selçuk Köse, Emre Salman, Zeljko Ignjatovic, Eby G. Friedman:
Pseudo-random clocking to enhance signal integrity. SoCC 2008: 47-50 - [c108]Mikhail Popovich, Eby G. Friedman:
Nanoscale on-chip decoupling capacitors. SoCC 2008: 51-54 - [c107]Alexander Lavzin, Mücahit Kozak, Eby G. Friedman:
A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators. SoCC 2008: 267-270 - [c106]Vasilis F. Pavlidis, Eby G. Friedman:
Physical Design Issues in 3-D Integrated Technologies. VLSI-SoC (Selected Papers) 2008: 1-21 - 2007
- [j48]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman:
Predictions of CMOS compatible on-chip optical interconnect. Integr. 40(4): 434-446 (2007) - [j47]Magdy A. El-Moursy, Eby G. Friedman:
Wire shaping of RLC interconnects. Integr. 40(4): 461-472 (2007) - [j46]Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman:
Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1114-1125 (2007) - [j45]Jonathan Rosenfeld, Eby G. Friedman:
Design Methodology for Global Resonant H-Tree Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 135-148 (2007) - [j44]Vasilis F. Pavlidis, Eby G. Friedman:
3-D Topologies for Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1081-1090 (2007) - [c105]Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. ICCAD 2007: 811-816 - [c104]Jonathan Rosenfeld, Eby G. Friedman:
Quasi-Resonant Interconnects: A Low Power Design Methodology. ISCAS 2007: 641-644 - [c103]Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
Substrate Noise Reduction Based On Noise Aware Cell Design. ISCAS 2007: 3227-3230 - [c102]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman:
On-chip optical interconnect for reduced delay uncertainty. Nano-Net 2007: 22 - 2006
- [j43]Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
Sizing CMOS inverters with Miller Effect and Threshold voltage Variations. J. Circuits Syst. Comput. 15(3): 437-454 (2006) - [j42]Weize Xu, Eby G. Friedman:
On-chip test circuit for measuring substrate and line-to-line coupling noise. IEEE J. Solid State Circuits 41(2): 474-482 (2006) - [j41]Guoqing Chen, Eby G. Friedman:
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 161-172 (2006) - [j40]Mikhail Popovich, Eby G. Friedman:
Decoupling capacitors for multi-voltage power distribution systems. IEEE Trans. Very Large Scale Integr. Syst. 14(3): 217-228 (2006) - [j39]Junmou Zhang, Eby G. Friedman:
Crosstalk modeling for coupled RLC interconnects with application to shield insertion. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 641-646 (2006) - [c101]Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu:
Maximum effective distance of on-chip decoupling capacitors in power distribution grids. ACM Great Lakes Symposium on VLSI 2006: 173-179 - [c100]Jonathan Rosenfeld, Eby G. Friedman:
Sensitivity evaluation of global resonant H-tree clock distribution networks. ACM Great Lakes Symposium on VLSI 2006: 192-197 - [c99]Guoqing Chen, Eby G. Friedman:
Effective capacitance of RLC loads for estimating short-circuit power. ISCAS 2006 - [c98]Magdy A. El-Moursy, Eby G. Friedman:
Optimum wire tapering for minimum power dissipation in RLC interconnects. ISCAS 2006 - [c97]Vasilis F. Pavlidis, Eby G. Friedman:
Via placement for minimum interconnect delay in three-dimensional (3D) circuits. ISCAS 2006 - [c96]Jonathan Rosenfeld, Eby G. Friedman:
Design methodology for global resonant H-tree clock distribution networks. ISCAS 2006 - [c95]Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman:
On-die decoupling capacitance: frequency domain analysis of activity radius. ISCAS 2006 - [c94]Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar:
Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. ISQED 2006: 159-164 - [c93]Vasilis F. Pavlidis, Eby G. Friedman:
3-D Topologies for Networks-on-Chip. SoCC 2006: 285-288 - [c92]Emre Salman, Eby G. Friedman, Radu M. Secareanu:
Substrate and Ground Noise Interactions in Mixed-Signal Circuits. SoCC 2006: 293-296 - 2005
- [j38]Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra:
Monolithic voltage conversion in low-voltage CMOS technologies. Microelectron. J. 36(9): 863-867 (2005) - [j37]Guoqing Chen, Eby G. Friedman:
An RLC interconnect model based on fourier analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 170-183 (2005) - [j36]Magdy A. El-Moursy, Eby G. Friedman:
Shielding effect of on-chip interconnect inductance. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 396-400 (2005) - [j35]Magdy A. El-Moursy, Eby G. Friedman:
Exponentially tapered H-tree clock distribution networks. IEEE Trans. Very Large Scale Integr. Syst. 13(8): 971-975 (2005) - [c91]Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny:
On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. ACM Great Lakes Symposium on VLSI 2005: 2-7 - [c90]Vasilis F. Pavlidis, Eby G. Friedman:
Interconnect delay minimization through interlayer via placement in 3-D ICs. ACM Great Lakes Symposium on VLSI 2005: 20-25 - [c89]Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva G. Narendra:
Cascode buffer for monolithic voltage conversion operating at high input supply voltages. ISCAS (1) 2005: 464-467 - [c88]Guoqing Chen, Eby G. Friedman:
Low power repeaters driving RLC interconnects with delay and bandwidth constraints. ISCAS (1) 2005: 596-599 - [c87]Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Virgilio Fernandez, Eby G. Friedman:
Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. ISCAS (1) 2005: 612-615 - [c86]Mikhail Popovich, Eby G. Friedman:
Noise coupling in multi-voltage power distribution systems with decoupling capacitors. ISCAS (1) 2005: 620-623 - [c85]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi:
Electrical and optical on-chip interconnects in scaled microprocessors. ISCAS (3) 2005: 2514-2517 - [c84]Guoqing Chen, Eby G. Friedman:
A Fourier series-based RLC interconnect model for periodic signals. ISCAS (4) 2005: 4126-4129 - [c83]Mikhail Popovich, Eby G. Friedman:
Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems. ISQED 2005: 334-339 - [c82]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi:
Predictions of CMOS compatible on-chip optical interconnect. SLIP 2005: 13-20 - [c81]Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin:
On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits. SoCC 2005: 309-312 - 2004
- [j34]Magdy A. El-Moursy, Eby G. Friedman:
Optimum wire sizing of RLC interconnect with repeaters . Integr. 38(2): 205-225 (2004) - [j33]Volkan Kursun, Siva G. Narendra, Vivek K. De, Eby G. Friedman:
Low-voltage-swing monolithic dc-dc conversion. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 241-248 (2004) - [j32]Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman:
Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. Very Large Scale Integr. Syst. 12(1): 67-78 (2004) - [j31]Andrey V. Mezhiba, Eby G. Friedman:
Scaling trends of on-chip power distribution noise. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 386-394 (2004) - [j30]Volkan Kursun, Eby G. Friedman:
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 485-496 (2004) - [j29]Andrey V. Mezhiba, Eby G. Friedman:
Impedance characteristics of power distribution grids in nanoscale integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1148-1155 (2004) - [j28]Magdy A. El-Moursy, Eby G. Friedman:
Power characteristics of inductive interconnect. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1295-1306 (2004) - [j27]Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
Complex +/-1 Multiplier Based on Signed-Binary Transformations. J. VLSI Signal Process. 38(1): 13-24 (2004) - [c80]Jonathan Rosenfeld, Mücahit Kozak, Eby G. Friedman:
A bulk-driven CMOS OTA with 68 dB DC gain. ICECS 2004: 5-8 - [c79]Boaz Shem-Tov, Mücahit Kozak, Eby G. Friedman:
A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applications. ICECS 2004: 113-116 - [c78]Mikhail Popovich, Eby G. Friedman:
Impedance characteristics of decoupling capacitors in multi-power distribution systems. ICECS 2004: 160-163 - [c77]Eby G. Friedman:
Challenges in ultra deep submicrometer high performance VLSI circuits. ICECS 2004: 238- - [c76]Dimitrios Velenis, Ramyashree Sundaresha, Eby G. Friedman:
Buffer sizing for delay uncertainty induced by process variations. ICECS 2004: 415-418 - [c75]Boaz Shem-Tov, Mücahit Kozak, Eby G. Friedman:
A high-speed CMOS op-amp design technique using negative Miller capacitance. ICECS 2004: 623-626 - [c74]Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
Low power flexible Rake receivers for WCDMA. ISCAS (4) 2004: 97-100 - [c73]Volkan Kursun, Eby G. Friedman:
Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. ISCAS (2) 2004: 417-420 - [c72]Junmou Zhang, Eby G. Friedman:
Decoupling technique and crosstalk analysis for coupled RLC interconnects. ISCAS (2) 2004: 521-524 - [c71]Junmou Zhang, Eby G. Friedman:
Effect of shield insertion on reducing crosstalk noise between coupled interconnects. ISCAS (2) 2004: 529-532 - [c70]Magdy A. El-Moursy, Eby G. Friedman:
Exponentially tapered H-tree clock distribution networks. ISCAS (2) 2004: 601-604 - [c69]Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman:
A low power thyristor-based CMOS programmable delay element. ISCAS (1) 2004: 769-772 - [c68]Mücahit Kozak, Eby G. Friedman:
Design and simulation of Fractional-N PLL frequency synthesizers. ISCAS (4) 2004: 780-783 - [c67]Volkan Kursun, Eby G. Friedman:
Forward body biased keeper for enhanced noise immunity in domino logic circuits. ISCAS (2) 2004: 917-920 - [c66]Volkan Kursun, Eby G. Friedman:
Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. ISQED 2004: 104-109 - [c65]Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. ISQED 2004: 517-521 - [c64]Dimitrios Velenis, Eby G. Friedman:
Buffer Sizing for Crosstalk Induced Delay Uncertainty. PATMOS 2004: 750-759 - [c63]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Clock tree layout design for reduced delay uncertainty. SoCC 2004: 179-180 - [c62]Mikhail Popovich, Eby G. Friedman:
Decoupling capacitors for power distribution systems with multiple power supply voltages. SoCC 2004: 331-334 - [c61]Guoqing Chen, Eby G. Friedman:
Low power repeaters driving RC interconnects with delay and bandwidth constraints. SoCC 2004: 335-339 - [c60]Junmou Zhang, Eby G. Friedman:
Mutual inductance modeling for multiple RLC interconnects with application to shield insertion. SoCC 2004: 344-347 - 2003
- [j26]David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster:
Dynamically Tuning Processor Resources with Adaptive Processing. Computer 36(12): 49-58 (2003) - [j25]Yehea I. Ismail, Eby G. Friedman:
On the Extraction of On-Chip Inductance. J. Circuits Syst. Comput. 12(1): 31-40 (2003) - [j24]Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 514-522 (2003) - [j23]Volkan Kursun, Eby G. Friedman:
Domino logic with variable threshold voltage keeper. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1080-1093 (2003) - [c59]Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075 - [c58]Magdy A. El-Moursy, Eby G. Friedman:
Optimum wire sizing of RLC interconnect with repeaters. ACM Great Lakes Symposium on VLSI 2003: 27-32 - [c57]Magdy A. El-Moursy, Eby G. Friedman:
Shielding effect of on-chip interconnect inductance. ACM Great Lakes Symposium on VLSI 2003: 165-170 - [c56]Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
Orthogonal code generator for 3G wireless transceivers. ACM Great Lakes Symposium on VLSI 2003: 229-232 - [c55]Magdy A. El-Moursy, Eby G. Friedman:
Power characteristics of inductive interconnect. ICECS 2003: 499-502 - [c54]Magdy A. El-Moursy, Eby G. Friedman:
Inductive interconnect width optimization for low power. ISCAS (5) 2003: 273-276 - [c53]Andrey V. Mezhiba, Eby G. Friedman:
Electrical characteristics of multi-layer power distribution grids. ISCAS (5) 2003: 473-476 - [c52]Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman:
Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. ISQED 2003: 279- - [c51]Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman:
Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic. IWSOC 2003: 70-75 - 2002
- [j22]Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman:
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. J. Circuits Syst. Comput. 11(3): 231-246 (2002) - [j21]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Inductance Effects in RLC Trees. J. Circuits Syst. Comput. 11(3): 305- (2002) - [j20]Yehea I. Ismail, Eby G. Friedman:
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 131-144 (2002) - [j19]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Retiming and clock scheduling for digital circuit optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 184-203 (2002) - [j18]Kevin T. Tang, Eby G. Friedman:
Simultaneous switching noise in on-chip CMOS power distribution networks. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 487-493 (2002) - [j17]Andrey V. Mezhiba, Eby G. Friedman:
Inductive properties of high-performance power distribution grids. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 762-776 (2002) - [c50]Andrey V. Mezhiba, Eby G. Friedman:
Properties of on-chip inductive current loops. ACM Great Lakes Symposium on VLSI 2002: 12-17 - [c49]Volkan Kursun, Eby G. Friedman:
Low swing dual threshold voltage domino logic. ACM Great Lakes Symposium on VLSI 2002: 47-52 - [c48]Boris D. Andreev, Eby G. Friedman, Edward L. Titlebaum:
Efficient implementation of a complex ±1 multiplier. ACM Great Lakes Symposium on VLSI 2002: 83-88 - [c47]Andrey V. Mezhiba, Eby G. Friedman:
Inductance/area/resistance tradeoffs in high performance power distribution grids. ISCAS (1) 2002: 101-104 - [c46]Weize Xu, Eby G. Friedman:
A substrate noise circuit for accurately testing mixed-signal ICs. ISCAS (1) 2002: 145-148 - [c45]Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev:
Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. ISCAS (1) 2002: 357-360 - [c44]Andrey V. Mezhiba, Eby G. Friedman:
Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits. ISQED 2002: 316-321 - [c43]Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman:
Managing static leakage energy in microprocessor functional units. MICRO 2002: 321-332 - [c42]Andrey V. Mezhiba, Eby G. Friedman:
Scaling trends of on-chip Power distribution noise. SLIP 2002: 47-53 - 2001
- [j16]Eby G. Friedman:
Clock distribution networks in synchronous digital integrated circuits. Proc. IEEE 89(5): 665-692 (2001) - [j15]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Exploiting the on-chip inductance in high-speed clock distribution networks. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 963-973 (2001) - [c41]Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise. ICECS 2001: 181-184 - [c40]Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman:
Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. ICECS 2001: 1021-1025 - [c39]Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425 - [c38]Kevin T. Tang, Eby G. Friedman:
Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. ISCAS (5) 2001: 463-466 - 2000
- [j14]Kevin T. Tang, Eby G. Friedman:
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections. Integr. 29(2): 131-165 (2000) - [j13]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Equivalent Elmore delay for RLC trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 83-97 (2000) - [j12]Yehea I. Ismail, Eby G. Friedman:
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 195-206 (2000) - [c37]Radu M. Secareanu, Eby G. Friedman:
Transparent repeaters. ACM Great Lakes Symposium on VLSI 2000: 63-66 - [c36]Kevin T. Tang, Eby G. Friedman:
Noise estimation due to signal activity for capacitively coupled CMOS logic gates. ACM Great Lakes Symposium on VLSI 2000: 171-176 - [c35]Kevin T. Tang, Eby G. Friedman:
Transient analysis of a CMOS inverter driving resistive interconnect. ISCAS 2000: 269-272 - [c34]Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system. ISCAS 2000: 277-280 - [c33]Kevin T. Tang, Eby G. Friedman:
Delay and power expressions characterizing a CMOS inverter driving an RLC load. ISCAS 2000: 283-286 - [c32]Yehea I. Ismail, Eby G. Friedman:
Sensitivity of interconnect delay to on-chip inductance. ISCAS 2000: 403-406
1990 – 1999
- 1999
- [j11]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Figures of merit to characterize the importance of on-chip inductance. IEEE Trans. Very Large Scale Integr. Syst. 7(4): 442-449 (1999) - [c31]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236 - [c30]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Equivalent Elmore Delay for RLC Trees. DAC 1999: 715-720 - [c29]Yehea I. Ismail, Eby G. Friedman:
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. DAC 1999: 721-724 - [c28]Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman:
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649 - [c27]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Inductance Effects in RLC Trees. Great Lakes Symposium on VLSI 1999: 56-59 - [c26]Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman:
Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. Great Lakes Symposium on VLSI 1999: 314-317 - [c25]Ivan S. Kourtev, Eby G. Friedman:
Clock skew scheduling for improved reliability via quadratic programming. ICCAD 1999: 239-243 - [c24]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Repeater insertion in tree structured inductive interconnect. ICCAD 1999: 420-424 - [c23]Radu M. Secareanu, Victor Adler, Eby G. Friedman:
Exploiting hysteresis in a CMOS buffer. ICECS 1999: 205-208 - [c22]Kevin T. Tang, Eby G. Friedman:
Peak crosstalk noise estimation in CMOS VLSI circuits. ICECS 1999: 1539-1542 - [c21]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Signal waveform characterization in RLC trees. ISCAS (6) 1999: 190-193 - [c20]Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner:
A universal CMOS voltage interface circuit. ISCAS (1) 1999: 242-245 - [c19]Radu M. Secareanu, Eby G. Friedman:
A high precision CMOS current mirror/divider. ISCAS (2) 1999: 314-317 - [c18]Yehea I. Ismail, Eby G. Friedman:
Repeater insertion in RLC lines for minimum propagation delay. ISCAS (6) 1999: 404-407 - [c17]Kevin T. Tang, Eby G. Friedman:
Peak noise prediction in loosely coupled interconnect [VLSI circuits]. ISCAS (1) 1999: 541-544 - [c16]Kevin T. Tang, Eby G. Friedman:
Interconnect coupling noise in CMOS VLSI circuits. ISPD 1999: 48-53 - [r1]Ivan S. Kourtev, Eby G. Friedman:
System Timing. The VLSI Handbook 1999 - 1998
- [j10]José Luis Neves, Eby G. Friedman:
Automated Synthesis of Skew-Based Clock Distribution Networks. VLSI Design 7(1): 31-57 (1998) - [c15]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Figures of Merit to Characterize the Importance of On-Chip Inductance. DAC 1998: 560-565 - [c14]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. Great Lakes Symposium on VLSI 1998: 39-44 - [c13]Victor Adler, Eby G. Friedman:
A repeater timing model and insertion algorithm to reduce delay in RC tree structures. ICECS 1998: 67-70 - [c12]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Transient power in CMOS gates driving LC transmission lines. ICECS 1998: 337-340 - [c11]Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Power dissipated by CMOS gates driving lossless transmission lines. ISLPED 1998: 139-142 - 1997
- [j9]Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.:
Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 105-120 (1997) - [j8]Eby G. Friedman:
High Performance Clock Distribution Networks. J. VLSI Signal Process. 16(2-3): 113-116 (1997) - [j7]José Luis Neves, Eby G. Friedman:
Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. J. VLSI Signal Process. 16(2-3): 149-161 (1997) - [j6]Kris Gaj, Eby G. Friedman, Marc J. Feldman:
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits. J. VLSI Signal Process. 16(2-3): 247-276 (1997) - 1996
- [j5]José Luis Neves, Eby G. Friedman:
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 286-291 (1996) - [c10]José Luis Neves, Eby G. Friedman:
Optimal Clock Skew Scheduling Tolerant to Process Variations. DAC 1996: 623-628 - 1995
- [j4]Brian S. Cherkauer, Eby G. Friedman:
Design of tapered buffers with local interconnect capacitance. IEEE J. Solid State Circuits 30(2): 151-155 (1995) - [j3]Brian S. Cherkauer, Eby G. Friedman:
A unified design methodology for CMOS tapered buffers. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 99-111 (1995) - [c9]José Luis Neves, Eby G. Friedman:
Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. ISCAS 1995: 1576-1579 - [c8]Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.:
Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. ISCAS 1995: 1748-1751 - 1994
- [j2]Brian S. Cherkauer, Eby G. Friedman:
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 100-114 (1994) - [c7]Tolga Soyata, Eby G. Friedman:
Retiming with non-zero clock skew, variable register, and interconnect delay. ICCAD 1994: 234-241 - [c6]Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan:
Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. ISCAS 1994: 1-6 - [c5]Brian S. Cherkauer, Eby G. Friedman:
Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. ISCAS 1994: 111-114 - [c4]José Luis Neves, Eby G. Friedman:
Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. ISCAS 1994: 175-178 - 1993
- [c3]Eby G. Friedman:
Clock Distribution Design in VLSI Circuits. An Overview. ISCAS 1993: 1475-1478 - [c2]Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.:
Integration of Clock Skew and Register Delays into a Retiming Algorithm. ISCAS 1993: 1483-1486 - [c1]Brian S. Cherkauer, Eby G. Friedman:
The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. ISCAS 1993: 2110-2113 - 1991
- [j1]Eby G. Friedman, James H. Mulligan Jr.:
Clock frequency and latency in synchronous digital systems. IEEE Trans. Signal Process. 39(4): 930-934 (1991)
Coauthor Index
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