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ORCIDCharles E. Stroud
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2010 – 2019
- 2011
[j17]Jie Qin, Joseph Cali, Bradley F. Dutton, George J. Starr, Fa Foster Dai, Charles E. Stroud:
Selective Spectrum Analysis for Analog Measurements. IEEE Trans. Ind. Electron. 58(10): 4960-4971 (2011)- 2010
- [j16]Bradley F. Dutton, Charles E. Stroud:
On-Line Single Event Upset Detection and Correction in Field Programmable Gate Array Configuration Memories. Int. J. Comput. Their Appl. 17(2): 59-69 (2010) - [c46]Charles E. Stroud, Bradley F. Dutton:
The First Clock Cycle Is A Real BIST. ESA 2010: 86-92
2000 – 2009
- 2009
- [j15]Mary D. Pulukuri, Charles E. Stroud:
On Built-In Self-Test for Adders. J. Electron. Test. 25(6): 343-346 (2009) - [c45]Bradley F. Dutton, Charles E. Stroud:
Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs. CATA 2009: 57-62 - [c44]Brooks R. Garrison, Daniel T. Milton, Charles E. Stroud:
Built-in Self-Test for Memory Resources in Virtex-4 Field Programmable Gate Arrays. CATA 2009: 63-68 - [c43]George J. Starr, J. M. Wersinger, Richard Chapman, Lloyd Riggs, Victor P. Nelson, John Klingelhoeffer, Charles E. Stroud:
Application of Embedded Systems in Low Earth Orbit for Measurement of Ionospheric Anomalies. ESA 2009: 9-15 - [c42]Bradley F. Dutton, Charles E. Stroud:
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs. ESA 2009: 149-155 - [c41]Bradley F. Dutton, Mustafa Ali, Charles E. Stroud, John Sunwoo:
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs. ESA 2009: 183-189 - [c40]George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, Foster F. Dai, Victor P. Nelson:
Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems. DFT 2009: 11-19 - [c39]Bradley F. Dutton, Charles E. Stroud:
Soft Core Embedded Processor Based Built-In Self-Test of FPGAs. DFT 2009: 29-37 - 2008
- [p1]Laung-Terng Wang, Charles E. Stroud, Kwang-Ting (Tim) Cheng:
Logic Testing. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j14]Jie Qin, Charles E. Stroud, Fa Foster Dai:
FPGA-Based Analog Functional Measurements for Adaptive Control in Mixed-Signal Systems. IEEE Trans. Ind. Electron. 54(4): 1885-1897 (2007) - [j13]John Marty Emmert, Charles E. Stroud, Miron Abramovici:
Online Fault Tolerance for FPGA Logic Blocks. IEEE Trans. Very Large Scale Integr. Syst. 15(2): 216-226 (2007) - [c38]Jie Qin, Charles E. Stroud, Foster F. Dai:
Noise Figure Measurement Using Mixed-Signal BIST. ISCAS 2007: 2180-2183 - 2006
- [j12]Jack R. Smith, Tian Xia, Charles E. Stroud:
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults. J. Electron. Test. 22(3): 239-253 (2006) - [j11]Foster F. Dai, Charles E. Stroud, Dayu Yang:
Automatic linearity and frequency response tests with built-in pattern generator and analyzer. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 561-572 (2006) - [c37]Daniel T. Milton, Sachin Dhingra, Charles E. Stroud:
Embedded Processor Based Built-In Self-Test and Diagnosis of Logic and Memory Resources in FPGAs. ESA 2006: 87-93 - [c36]Lee Lerner, Charles E. Stroud:
An Architecture for Fail-Silent Operation of FPGAs and Configurable SoCs. ESA 2006: 176-182 - [c35]Charles E. Stroud, Dayu Yang, Foster F. Dai:
Analog frequency response measurement in mixed-signal systems. ISCAS 2006 - 2005
- [c34]Charles E. Stroud, Srinivas M. Garimella, John Sunwoo:
On-Chip BIST-Based Diagnosis of Embedded Programmable Logic Cores in System-on-Chip Devices. CATA 2005: 308-313 - [c33]Srinivas M. Garimella, Charles E. Stroud:
Built-In Self-Test and Diagnosis of Multiple Embedded Cores in SoCs. ESA 2005: 130-136 - [c32]Dayu Yang, Foster F. Dai, Charles E. Stroud:
Built-in self-test for automatic analog frequency response measurement. ISCAS (3) 2005: 2208-2211 - 2004
- [j10]Miron Abramovici, Charles E. Stroud, John Marty Emmert:
Online BIST and BIST-based diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 12(12): 1284-1294 (2004) - [c31]Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi:
Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. ITC 2004: 271-280 - [c30]Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris:
Built-In Self-Test for System-on-Chip: A Case Study. ITC 2004: 837-846 - 2003
- [j9]Miron Abramovici, Charles E. Stroud:
BIST-Based Delay-Fault Testing in FPGAs. J. Electron. Test. 19(5): 549-558 (2003) - [c29]Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter:
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. ITC 2003: 1258-1267 - 2002
- [c28]Miron Abramovici, Charles E. Stroud, John Marty Emmert:
Using embedded FPGAs for SoC yield improvement. DAC 2002: 713-724 - [c27]Miron Abramovici, Charles E. Stroud:
BIST-Based Delay-Fault Testing in FPGAs. IOLTW 2002: 131-134 - [c26]Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici:
BIST-Based Diagnosis of FPGA Interconnect. ITC 2002: 618-627 - 2001
- [j8]Miron Abramovici, Charles E. Stroud:
BIST-based test and diagnosis of FPGA logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 159-172 (2001) - [c25]John Marty Emmert, Stanley Baumgart, Pankaj Kataria, Andrew M. Taylor, Charles E. Stroud, Miron Abramovici:
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. DFT 2001: 445-454 - [c24]Miron Abramovici, John Marty Emmert, Charles E. Stroud:
Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. Evolvable Hardware 2001: 73-92 - [c23]Miron Abramovici, Charles E. Stroud, Matthew Lashinsky, Jeremy Nall, John Marty Emmert:
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. IOLTW 2001: 27-33 - [c22]Henry Chang, Steve Dollens, Gordon W. Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham:
Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? VTS 2001: 415-416 - 2000
- [j7]Charles E. Stroud, James R. Bailey, Johan R. Emmert:
A New Method for Testing Re-Programmable PLAs. J. Electron. Test. 16(6): 635-640 (2000) - [c21]John Marty Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici:
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. FCCM 2000: 165-174 - [c20]John Marty Emmert, Charles E. Stroud, Jason A. Cheatham, Andrew M. Taylor, Pankaj Kataria, Miron Abramovici:
Performance Penalty for Fault Tolerance in Roving STARs. FPL 2000: 545-554 - [c19]Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John Marty Emmert:
Improving On-Line BIST-Based Diagnosis for Roving STARs. IOLTW 2000: 31-39 - [c18]Charles E. Stroud, John Marty Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic:
Bridging fault extraction from physical design data for manufacturing test development. ITC 2000: 760-769 - [c17]Miron Abramovici, Charles E. Stroud:
DIST-based detection and diagnosis of multiple faults in FPGAs. ITC 2000: 785-794
1990 – 1999
- 1999
- [c16]Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma:
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. ITC 1999: 973-982 - [c15]Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles E. Stroud:
Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access. VTS 1999: 413-419 - 1998
- [c14]Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici:
Built-in self-test of FPGA interconnect. ITC 1998: 404-411 - [c13]Charles E. Stroud, Joe K. Tannehill Jr.:
Applying Built-In Self-Test to Majority Voting Fault Tolerant Circuits. VTS 1998: 303-308 - 1997
- [c12]Charles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri
, I. Kim, Subhajit Roy, S. Wu:
A Parameterized VHDL Library for On-Line Testing. ITC 1997: 479-488 - [c11]Charles E. Stroud, Eric Lee, Miron Abramovici:
BIST-Based Diagnostics of FPGA Logic Blocks. ITC 1997: 539-547 - 1996
- [c10]Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici:
Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. FPGA 1996: 107-113 - [c9]Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici:
Using ILA Testing for BIST in FPGAs. ITC 1996: 68-75 - [c8]Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici:
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). VTS 1996: 387-392 - 1995
- [j6]T. Raju Damarla, Charles E. Stroud, Avinash Sathaye:
Multiple error detection and identification via signature analysis. J. Electron. Test. 7(3): 193-207 (1995) - [c7]T. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud:
A built-in self test scheme for VLSI. ASP-DAC 1995 - [c6]Charles E. Stroud, T. Raju Damarla:
Improving the efficiency of error identification via signature analysis. VTS 1995: 244-249 - 1994
- [j5]Charles E. Stroud:
Reliability of majority voting based VLSI fault-tolerant circuits. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 516-521 (1994) - 1993
- [j4]Charles E. Stroud, Ahmed E. Barbour:
Testability and test generation for majority voting fault-tolerant circuits. J. Electron. Test. 4(3): 201-214 (1993) - 1991
- [c5]Charles E. Stroud:
Built-In Self-Test for High-Speed Data-Path Circuitry. ITC 1991: 47-56 - [c4]Charles E. Stroud:
Distractions in Design for Testability and Built-Is Self-Test. ITC 1991: 1112 - 1990
- [c3]Charles E. Stroud, Ahmed E. Barbour:
Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral Models. ICPP (1) 1990: 470-473
1980 – 1989
- 1989
- [c2]Charles E. Stroud, Ahmed E. Barbour:
Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant Circuits. ITC 1989: 812-818 - 1988
- [j3]Charles E. Stroud, Ronald R. Munoz, David A. Pierce:
Behavioral model synthesis with Cones. IEEE Des. Test 5(3): 22-30 (1988) - [j2]Charles E. Stroud:
Automated BIST for sequential logic synthesis. IEEE Des. Test 5(6): 22-32 (1988) - [c1]Charles E. Stroud:
An Automated BIST Approach for General Sequential Logic Synthesis. DAC 1988: 3-8 - 1986
- [j1]Sunil K. Jain, Charles E. Stroud:
Built-in Self Testing of Embedded Memories. IEEE Des. Test 3(5): 27-37 (1986)
Coauthor Index
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