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2020 – today
- 2024
[c51]Shun Nagasaki
, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System. CF 2024- [c50]Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. CHI Extended Abstracts 2024: 395:1-395:5 - [c49]Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
Branch Divergence-Aware Flexible Approximating Technique on GPUs. COOL CHIPS 2024: 1-6 - [c48]Shoi To, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
DataPipettor: Touch-Based Information Transfer Interface Using Proximity Wireless Communication. UIST (Adjunct Volume) 2024: 94:1-94:3 - 2023
- [j11]Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System. IEEE Des. Test 40(6): 18-29 (2023) - [j10]Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Principal Factor of Performance in Decoupled Front-End. IEICE Trans. Inf. Syst. 106(12): 1960-1968 (2023) - [j9]Rin Oishi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
FPGA-based Garbling Accelerator with Parallel Pipeline Processing. IEICE Trans. Inf. Syst. 106(12): 1988-1996 (2023) - [c47]Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. CC 2023: 73-84 - [c46]Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. DATE 2023: 1-2 - [c45]Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. ISCAS 2023: 1-5 - [c44]Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. MICRO 2023: 1-16 - [c43]Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. SenSys 2023: 502-503 - [c42]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. SenSys 2023: 554-555 - [c41]Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers. SPLASH Companion 2023: 61-62 - [c40]Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. UIST (Adjunct Volume) 2023: 25:1-25:3 - 2022
- [c39]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. ASP-DAC 2022: 98-99 - [c38]Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
T-SKID: Predicting When to Prefetch Separately from Address Prediction. DATE 2022: 1389-1394 - [c37]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. MCSoC 2022: 78-84 - 2021
- [j8]Junichiro Kadomoto, Takuya Sasatani, Koya Narumi, Naoto Usami, Hidetsugu Irie, Shuichi Sakai, Yoshihiro Kawahara:
Toward Wirelessly Cooperated Shape-Changing Computing Particles. IEEE Pervasive Comput. 20(3): 9-17 (2021) - [c36]Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai:
Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. ICCD 2021: 74-82 - [c35]Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. ICCD 2021: 88-92 - [c34]Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. ICCD 2021: 400-408 - [c33]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Multiport Register File Design for High-Performance Embedded Cores. MCSoC 2021: 281-286 - 2020
- [c32]Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai:
An Inductively Coupled Wireless Bus for Chiplet-Based Systems. ASP-DAC 2020: 9-10 - [c31]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. AsianCHI@CHI 2020: 7 - [c30]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. COOL CHIPS 2020: 1-3 - [c29]Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
A High-Performance Out-of-Order Soft Processor Without Register Renaming. FPL 2020: 73-78 - [c28]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. ICCD 2020: 589-596
2010 – 2019
- 2019
- [c27]Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. ICCD 2019: 100-108 - [c26]Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima:
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. FPT 2019: 63-71 - 2018
- [c25]Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. FPT 2018: 374-377 - [c24]Toru Koizumi, Satoshi Nakae, Akifumi Fukuda, Hidetsugu Irie, Shuichi Sakai:
Reduction of Instruction Increase Overhead by STRAIGHT Compiler. CANDAR Workshops 2018: 92-98 - [c23]Takahiro Yamada, Hidetsugu Irie, Masahiro Kunitake, Eiji Nagano, Shuichi Sakai:
Estimating driver's readiness by understanding driving posture. ICCE 2018: 1-4 - [c22]Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai:
STRAIGHT: Hazardless Processor Architecture Without Register Renaming. MICRO 2018: 121-133 - 2017
- [c21]Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai:
Accelerating Integrity Verification on Secure Processors by Promissory Hash. PRDC 2017: 20-29 - 2016
- [c20]Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai:
"Stubborn" strategy to mitigate remaining cache misses. ICCD 2016: 388-391 - [c19]Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai:
High-Accuracy Joint Position Estimation and Posture Detection System for Driving. MobiQuitous (Adjunct Proceedings) 2016: 219-224 - 2015
- [j7]Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga:
Design and Evaluation of a Configurable Query Processing Hardware for Data Streams. IEICE Trans. Inf. Syst. 98-D(12): 2207-2217 (2015) - 2014
- [c18]Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga:
Accelerating OLAP Workload on Interconnected FPGAs with Flash Storage. CANDAR 2014: 440-446 - [c17]Masato Yoshimi, Ryu Kudo, Yasin Oge, Yuta Terada, Hidetsugu Irie, Tsutomu Yoshinaga:
An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications. MCSoC 2014: 289-296 - 2013
- [j6]Cisse Ahmadou Dit Adi, Michihiro Koibuchi, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga:
A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation. IEICE Trans. Inf. Syst. 96-D(12): 2545-2554 (2013) - [c16]Hirotaka Kashihara, Hiroki Shimizu, Hiroyoshi Houchi, Masato Yoshimi, Tsutomu Yoshinaga, Hidetsugu Irie:
A real-time gait improvement tool using a smartphone. AH 2013: 243 - [c15]Yasin Oge, Masato Yoshimi, Takefumi Miyoshi, Hideyuki Kawashima, Hidetsugu Irie, Tsutomu Yoshinaga:
An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA. CANDAR 2013: 112-121 - [c14]Takuma Nakajima, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga:
Sharing Computing Resources with Virtual Machines by Transparent Data Access. CANDAR 2013: 359-365 - 2012
- [j5]Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga:
Using Cacheline Reuse Characteristics for Prefetcher Throttling. IEICE Trans. Inf. Syst. 95-D(12): 2928-2938 (2012) - [c13]Takefumi Miyoshi, Hidetsugu Irie, Keigo Shima, Hiroki Honda, Masaaki Kondo, Tsutomu Yoshinaga:
FLAT: a GPU programming framework to provide embedded MPI. GPGPU@ASPLOS 2012: 20-29 - [c12]Akira Egashira, Shunji Satoh, Hidetsugu Irie, Tsutomu Yoshinaga:
Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion. ICNC 2012: 130-136 - [c11]Hidetsugu Irie, Daisuke Fujiwara, Kazuki Majima, Tsutomu Yoshinaga:
STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers. ICNC 2012: 336-342 - [c10]Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga:
Throttling Control for Bufferless Routing in On-chip Networks. MCSoC 2012: 37-44 - 2011
- [j4]Junichi Ohmura, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga:
Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster. IEICE Trans. Inf. Syst. 94-D(12): 2319-2327 (2011) - [j3]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga:
An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. Int. J. Netw. Comput. 1(2): 244-259 (2011) - [c9]Hidetsugu Irie, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, Tsutomu Yoshinaga:
CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection. ICNC 2011: 127-133 - [c8]Junichi Ohmura, Akira Egashira, Shunji Satoh, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga:
Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation. ICNC 2011: 228-234 - 2010
- [c7]Takefumi Miyoshi, Kenji Kise, Hidetsugu Irie, Tsutomu Yoshinaga:
CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. ICNC 2010: 71-77 - [c6]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga:
An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161 - [c5]Qin Wang, Junichi Ohmura, Axida Shan, Takefumi Miyoshi, Hidetsugu Irie, Tsutomu Yoshinaga:
Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster. ICNC 2010: 243-248 - [c4]Cisse Ahmadou Dit Adi, Ping Qiu, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga:
OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip. IWIA 2010: 3-10
2000 – 2009
- 2008
- [j2]Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie:
Ultra Dependable Processor. IEICE Trans. Electron. 91-C(9): 1386-1393 (2008) - [c3]Shinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita:
Low-Complexity Bypass Network Using Small RAM. CDES 2008: 153-159 - 2007
- [j1]Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai:
Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Comput. Archit. News 35(5): 25-31 (2007) - [c2]Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai:
Utilization of SECDED for soft error and variation-induced defect tolerance in caches. DATE 2007: 1134-1139 - 2006
- [c1]Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai:
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC 2006: 165-172
Coauthor Index
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