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ORCIDCameron D. Patterson
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- affiliation: Virginia Tech
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2010 – 2019
- 2019
[j8]Miao Yao
, Matt Carrick, Munawwar M. Sohul, Vuk Marojevic, Cameron D. Patterson, Jeffrey H. Reed:
Semidefinite Relaxation-Based PAPR-Aware Precoding for Massive MIMO-OFDM Systems. IEEE Trans. Veh. Technol. 68(3): 2229-2243 (2019)- 2018
- [j7]Vivek Venugopalan, Cameron D. Patterson:
Surveying the Hardware Trojan Threat Landscape for the Internet-of-Things. J. Hardw. Syst. Secur. 2(2): 131-141 (2018) - 2017
- [c27]Vivek Venugopalan, Cameron D. Patterson:
Architectural refinements for enhancing trust and securing cyber-physical systems. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2017: 1-8 - 2016
- [c26]Vivek Venugopalan, Cameron D. Patterson, Devu Manikantan Shila:
Detecting and thwarting hardware trojan attacks in cyber-physical systems. CNS 2016: 421-425 - [c25]Pallavi P. Deshmukh, Cameron D. Patterson, William T. Baumann:
A hands-on modular laboratory environment to foster learning in control system security. FIE 2016: 1-9 - 2015
- [c24]Kevin G. Lyn, Lee W. Lerner, Christopher J. McCarty, Cameron D. Patterson:
The Trustworthy Autonomic Interface Guardian Architecture for Cyber-Physical Systems. CIT/IUCC/DASC/PICom 2015: 1803-1810 - [c23]N. Teja Chiluvuri, Omkar A. Harshe, Cameron D. Patterson, William T. Baumann:
Using Heterogeneous Computing to Implement a Trust Isolated Architecture for Cyber-Physical Control Systems. CPSS@ASIACSS 2015: 25-35 - [c22]Devu Manikantan Shila, Vivek Venugopalan, Cameron D. Patterson:
FIDES: Enhancing trust in reconfigurable based hardware systems. HPEC 2015: 1-7 - [c21]Devu Manikantan Shila, Vivek Venugopalan, Cameron D. Patterson:
Unraveling the Security Puzzle: A Distributed Framework to Build Trust in FPGAs. NSS 2015: 95-111 - [i1]Devu Manikantan Shila, Vivek Venugopalan, Cameron D. Patterson:
Enhancing Trust in Reconfigurable Based Hardware Systems with Tags and Monitors. IACR Cryptol. ePrint Arch. 2015: 441 (2015) - 2014
- [j6]Yousef Iskander, Cameron D. Patterson, Stephen D. Craven:
High-Level Abstractions and Modular Debugging for FPGA Design Validation. ACM Trans. Reconfigurable Technol. Syst. 7(1): 2:1-2:22 (2014) - [c20]Lee W. Lerner, Zane R. Franklin, William T. Baumann, Cameron D. Patterson:
Application-Level Autonomic Hardware to Predict and Preempt Software Attacks on Industrial Control Systems. DSN 2014: 136-147 - [c19]Lee W. Lerner, Zane R. Franklin, William T. Baumann, Cameron D. Patterson:
Using high-level synthesis and formal analysis to predict and preempt attacks on industrial control systems. FPGA 2014: 209-212 - 2012
- [c18]Mohammed M. Farag, Lee W. Lerner, Cameron D. Patterson:
Interacting with Hardware Trojans over a network. HOST 2012: 69-74 - [c17]Lee W. Lerner, Mohammed M. Farag, Cameron D. Patterson:
Run-time prediction and preemption of configuration attacks on embedded process controllers. SECURIT 2012: 135-144 - 2011
- [c16]Mohammed M. Farag, Lee W. Lerner, Cameron D. Patterson:
Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement. FPL 2011: 207-212 - [c15]Yousef Iskander, Cameron D. Patterson, Stephen D. Craven:
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug. FPL 2011: 518-523 - 2010
- [j5]Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong:
MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip. IET Comput. Digit. Tech. 4(3): 159-169 (2010) - [c14]Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tony Frangieh, Yousef Iskander, Stephen D. Craven, Cameron D. Patterson:
Accelerating FPGA development through the automatic parallel application of standard implementation tools. FPT 2010: 53-60 - [c13]Yousef Iskander, Stephen D. Craven, Athira Chandrasekharan, Sureshwar Rajagopalan, Guruprasad Subbarayan, Tannous Frangieh, Cameron D. Patterson:
Using partial reconfiguration and high-level models to accelerate FPGA design validation. FPT 2010: 341-344 - [c12]Tannous Frangieh, Athira Chandrasekharan, Sureshwar Rajagopalan, Yousef Iskander, Stephen D. Craven, Cameron D. Patterson:
PATIS: Using partial configuration to improve static FPGA design productivity. IPDPS Workshops 2010: 1-8
2000 – 2009
- 2009
- [j4]Allen B. MacKenzie, Jeffrey H. Reed, Peter M. Athanas, Charles W. Bostian, R. Michael Buehrer, Luiz A. DaSilva, Steven W. Ellingson, Y. Thomas Hou, Michael S. Hsiao, Jung-Min Park, Cameron D. Patterson, Sanjay Raman, Claudio R. C. M. da Silva:
Cognitive Radio and Networking Research at Virginia Tech. Proc. IEEE 97(4): 660-688 (2009) - [j3]Cameron D. Patterson, Peter Athanas, Matthew Shelburne, John W. Bowen, Jorge Surís, T. Dunham, J. Rice:
Slotless module-based reconfiguration of embedded FPGAs. ACM Trans. Embed. Comput. Syst. 9(1): 6:1-6:26 (2009) - [j2]Cameron D. Patterson, Steven W. Ellingson, Brian S. Martin, K. Deshpande, John H. Simonetti, Michael Kavic, Sean E. Cutchin:
Searching for Transient Pulses with the ETA Radio Telescope. ACM Trans. Reconfigurable Technol. Syst. 1(4): 20:1-20:19 (2009) - [c11]Paul E. Marks, Cameron D. Patterson:
Data streaming and simd support for the microblaze architecture. FPGA 2009: 277 - 2008
- [j1]Aric D. Blumer, Cameron D. Patterson:
Exploiting Process Locality of Reference in RTL Simulation Acceleration. EURASIP J. Embed. Syst. 2008 (2008) - [c10]Jorge Surís, Cameron D. Patterson, Peter Athanas:
An efficient run-time router for connecting modules in FPGAS. FPL 2008: 125-130 - [c9]Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong:
Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip. FPL 2008: 257-262 - 2007
- [c8]Aric D. Blumer, Henning S. Mortveit, Cameron D. Patterson:
Formal Modeling of Process Migration. FPL 2007: 104-110 - [c7]Peter M. Athanas, John W. Bowen, T. Dunham, Cameron D. Patterson, J. Rice, Matthew Shelburne, Jorge Surís, Mark B. Bucciero, Jonathan Graf:
Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing. FPL 2007: 513-516 - [c6]Aric D. Blumer, Cameron D. Patterson:
Hardware/Software Process Migration and RTL Simulation. FPL 2007: 585-588 - [c5]Cameron D. Patterson, Brian S. Martin, Steven W. Ellingson, John H. Simonetti, Sean E. Cutchin:
FPGA Cluster Computing in the ETA Radio Telescope. FPT 2007: 25-32 - [c4]Peter M. Athanas, Cameron D. Patterson:
A Holistic Approach Towards a Unified CpE Laboratory Platform. MSE 2007: 73-74 - 2006
- [c3]Stephen D. Craven, Cameron D. Patterson, Peter M. Athanas:
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays. HICSS 2006 - 2004
- [c2]Jesse Hunter, Peter Athanas, Cameron D. Patterson:
VTSim: A Virtex-II Device Simulator. ERSA 2004: 297-298 - [c1]Alexandra Poetter, Jesse Hunter, Cameron D. Patterson, Peter M. Athanas, Brent E. Nelson, Neil Steiner:
JHDLBits: The Merging of Two Worlds. FPL 2004: 414-423
Coauthor Index
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