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ORCIDHyojin Choi
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2020 – today
- 2021
[c9]Hyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi:
Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs. DAC 2021: 523-528
2010 – 2019
- 2015
- [c8]Min Baek, Hwan Lee, Hyojin Choi, Kyunbyoung Ko:
Poster: Development of ICA algorithm for V2X communications by using PreScan. VNC 2015: 167-168 - [c7]Seokil Song, Taein Jeon, Eungjin Kim, Jinsu Kim, Dojin Choi, Yeona Kim, Hyojin Choi, Kyunbyoung Ko, Cheol Mun:
Demo: Human-Interactive Hardware-In-the-Loop Simulator for Cooperative Intelligent Transportation Systems and services. VNC 2015: 169-170 - 2012
- [c6]Hyojin Choi, Jae-Woo Ahn, Wonyong Sung:
Reducing off-chip memory traffic by selective cache management scheme in GPGPUs. GPGPU@ASPLOS 2012: 110-119 - [c5]Hyojin Choi, Kyuyeon Hwang
, Jae-Woo Ahn, Wonyong Sung:
A simulation-based study for DRAM power reduction strategies in GPGPUs. ISCAS 2012: 1343-1346 - [c4]Su-Jin Cho, Jae-Woo Ahn, Hyojin Choi, Wonyong Sung:
Performance analysis of multi-bank DRAM with increased clock frequency. ISCAS 2012: 2477-2480 - 2011
- [c3]Hyojin Choi, Jongbok Lee, Wonyong Sung:
Memory access pattern-aware DRAM performance model for multi-core systems. ISPASS 2011: 66-75 - 2010
- [j2]Hyojin Choi, Wei Liu, Wonyong Sung:
VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 843-847 (2010)
2000 – 2009
- 2008
- [j1]Wonchul Lee, Hyojin Choi, Wonyong Sung:
Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP. J. Signal Process. Syst. 51(3): 289-302 (2008) - 2007
- [c2]Hyojin Choi, Wonchul Lee, Wonyong Sung:
Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding. ISCAS 2007: 2898-2901 - [c1]Wonchul Lee, Hyojin Choi, Wonyong Sung:
Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor. SiPS 2007: 169-174
Coauthor Index
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