default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDNanjian Wu
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j54]Fuming Lei, Xu Yang, Jian Liu, Runjiang Dou, Nanjian Wu:
DT-SCNN: dual-threshold spiking convolutional neural network with fewer operations and memory access for edge applications. Frontiers Comput. Neurosci. 18 (2024)- [j53]Xu Yang
, Chunhe Yao, Lei Kang, Qian Luo, Nan Qi, Runjiang Dou, Shuangming Yu, Peng Feng, Zhongming Wei, Jian Liu, Kaiyou Wang, Nanjian Wu, Liyuan Liu:
A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision. IEEE J. Solid State Circuits 59(6): 1883-1898 (2024) - [j52]Min Liu, Ziteng Cai, Zhe Wang, Shaohua Zhou, Man-Kay Law, Jian Liu, Jianguo Ma, Nanjian Wu, Liyuan Liu:
A 3 THz CMOS Image Sensor. IEEE J. Solid State Circuits 59(9): 2934-2947 (2024) - [j51]Zhe Wang, Xu Yang, Na Tian, Min Liu, Ziteng Cai, Peng Feng, Runjiang Dou, Shuangming Yu, Nanjian Wu, Jian Liu, Liyuan Liu:
A 64 × 128 3D-Stacked SPAD Image Sensor for Low-Light Imaging. Sensors 24(13): 4358 (2024) - [j50]Siyuan Wei, Ke Ning, Lei Kang, Xuemin Zheng, Mingxin Zhao, Mengmeng Xu, Shuyu Wang, Xuanzhe Xu, Runjiang Dou, Shuangming Yu, Xu Yang, Jian Liu, Cong Shi, Nanjian Wu, Liyuan Liu:
A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 740-753 (2024) - [j49]Cong Shi, Xiang Fu, Haibing Wang, Yingcheng Lin, Ying Jiang, Liyuan Liu, Nanjian Wu, Min Tian:
Ghost Reservoir: A Memory-Efficient Low-Power and Real-Time Neuromorphic Processor of Liquid State Machine With On-Chip Learning. IEEE Trans. Circuits Syst. II Express Briefs 71(10): 4526-4530 (2024) - [c66]Xinyu Shen, Zhao Zhang, Yong Chen, Yixi Li, Yidan Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. CICC 2024: 1-2 - [c65]Yang Min, Yi Zhang, Tao Yang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Yonghui Lin, Huiyao Peng, Jingbo Shi, Nan Qi:
A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission. ISCAS 2024: 1-4 - 2023
- [j48]Cong Shi, Junxian He, Shrinivas J. Pundlik, Xichuan Zhou, Nanjian Wu, Gang Luo:
Low-cost real-time VLSI system for high-accuracy optical flow estimation using biological motion features and random forests. Sci. China Inf. Sci. 66(5) (2023) - [j47]Leyi Chen, Cong Shi, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Min Tian:
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4249-4259 (2023) - [j46]Sikai Chen, Mingyang You, Yunqi Yang, Ye Jin, Ziyi Lin, Yihong Li, Leliang Li, Guike Li, Yujun Xie, Zhao Zhang, Binhao Wang, Ningfeng Tang, Faju Liu, Zheyu Fang, Jian Liu, Nanjian Wu, Yong Chen, Liyuan Liu, Ninghua Zhu, Ming Li, Nan Qi:
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4271-4282 (2023) - [j45]Mengmeng Xu, Zhongxing Zhang, Honglong Li, Qian Luo, Runjiang Dou, Liyuan Liu, Jian Liu, Nanjian Wu:
Hierarchical Parallel Vision Processor for High-Speed Ship Detection. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1164-1168 (2023) - [j44]Lei Kang, Xu Yang, Chi Zhang, Shuangming Yu, Runjiang Dou, Wenchang Li, Cong Shi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 24.3 μJ/Image SNN Accelerator for DVS-Gesture With WS-LOS Dataflow and Sparse Methods. IEEE Trans. Circuits Syst. II Express Briefs 70(11): 4226-4230 (2023) - [c64]Zhengqing Zhong, Tengxiao Wang, Haibing Wang, Zhihua Zhou, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi:
Live Demonstration: Face Recognition at The Edge Using Fast On-Chip Deep Learning Neuromorphic Chip. AICAS 2023: 1-2 - [c63]Yixi Li, Zhao Zhang, Yong Chen, Xinyu Shen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. A-SSCC 2023: 1-3 - [c62]Han Liu, Nan Qi, Donglai Lu, Zizheng Dong, Zhihan Zhang, Jian He, Guike Li, Leliang Li, Ye Liu, Ziyue Dang, Daigao Chen, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Liyuan Liu:
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. A-SSCC 2023: 1-3 - [c61]Tengxiao Wang, Min Tian, Zhengqing Zhong, Haibing Wang, Junxian He, Fang Tang, Xichuan Zhou, Shuangming Yu, Nanjian Wu, Liyuan Liu, Cong Shi:
MorphBungee: A 65nm 7.2mm2 27μJ/image Digital Edge Neuromorphic Chip with On-Chip 802 Frame/s Multi-Layer Spiking Neural Network Learning. A-SSCC 2023: 1-3 - [c60]Yidan Zhang, Zhao Zhang, Yiqing Xu, Xinyu Shen, Nan Qi, Nanjian Wu, Jian Liu, Liyuan Liu:
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain. A-SSCC 2023: 1-3 - [c59]Zhaoyu Zhang, Zhao Zhang, Yong Chen, Guoqing Wang, Xinyu Shen, Nan Qi, Guike Li, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu:
A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE. ESSCIRC 2023: 177-180 - [c58]Xinyu Shen, Zhao Zhang, Guike Li, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. ESSCIRC 2023: 257-260 - [c57]Fuming Lei, Xu Yang, Jian Liu, Nanjian Wu, Cong Shi, Runjiang Dou, Liyuan Liu:
A Lightweight Integer-STBP On-Chip Learning Method of Spiking Neural Networks For Edge Processors. ICTA 2023: 1-2 - [c56]Huanhui Zhang, Xu Yang, Zhe Wang, Shuangming Yu, Peng Feng, Jian Liu, Nanjian Wu, Runjiang Dou, Liyuan Liu:
A 128×128 15µm-Pitch DROIC with Pixel-Level 14-Bit ADC. ICTA 2023: 1-2 - [c55]Guoqing Wang, Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Jian Liu, Nanjian Wu, Liyuan Liu:
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. ICTA 2023: 120-121 - [c54]Jingbo Shi, Han Liu, Tao Yang, Ming Jin, Haowen Shu, Fenghe Yang, Lei Shi, Yuansheng Tao, Jianrui Deng, Ruixuan Chen, Changhao Han, Jian Liu, Nanjian Wu, Nan Qi, Liyuan Liu:
An 800G Integrated Silicon-Photonic Transmitter based on 16-Channel Mach-Zehnder Modulator and Co-Designed 5.35pJ/bit CMOS Drivers. ISCAS 2023: 1-4 - [c53]Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Nanjian Wu, Liyuan Liu:
A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. ISSCC 2023: 86-87 - [c52]Min Liu, Ziteng Cai, Shaohua Zhou, Man-Kay Law, Jian Liu, Jianguo Ma, Nanjian Wu, Liyuan Liu:
A 16.4kPixel 3.08-to-3.86THz Digital Real-Time CMOS Image Sensor with 73dB Dynamic Range. ISSCC 2023: 98-99 - [c51]Zhao Zhang, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j43]Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi:
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. IEEE J. Solid State Circuits 57(3): 767-780 (2022) - [j42]Li Cheng, Xuemin Zheng, Mingxin Zhao, Runjiang Dou, Shuangming Yu, Nanjian Wu, Liyuan Liu:
SiamMixer: A Lightweight and Hardware-Friendly Visual Object-Tracking Network. Sensors 22(4): 1585 (2022) - [j41]Haibing Wang, Zhen He, Tengxiao Wang, Junxian He, Xichuan Zhou, Ying Wang, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi:
TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity. IEEE Trans. Biomed. Circuits Syst. 16(4): 636-650 (2022) - [j40]Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, Nan Qi:
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1159-1170 (2022) - [j39]Jian He, Donglai Lu, Haiyun Xue, Sikai Chen, Han Liu, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Nanjian Wu, Ningmei Yu, Fengman Liu, Xi Xiao, Yong Chen, Nan Qi:
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4345-4357 (2022) - [j38]Zhen He, Cong Shi, Tengxiao Wang, Ying Wang, Min Tian, Xichuan Zhou, Ping Li, Liyuan Liu, Nanjian Wu, Gang Luo:
A Low-Cost FPGA Implementation of Spiking Extreme Learning Machine With On-Chip Reward-Modulated STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1657-1661 (2022) - [j37]Ke Ning, Mingxin Zhao, Chunhe Yao, Xuemin Zheng, Mengmeng Xu, Nanjian Wu, Liyuan Liu, Shuangming Yu:
A High-Speed NMS Coprocessor for Lightweight Ship Detection Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1677-1681 (2022) - [j36]Xuemin Zheng, Li Cheng, Mingxin Zhao, Qian Luo, Honglong Li, Runjiang Dou, Shuangming Yu, Nanjian Wu, Liyuan Liu:
ViP: A Hierarchical Parallel Vision Processor for Hybrid Vision Chip. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2957-2961 (2022) - [j35]Hongtao Zhou, Runjiang Dou, Li Cheng, Jian Liu, Nanjian Wu:
A Provisional Labels-Reduced, Real-Time Connected Component Labeling Algorithm for Edge Hardware. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2997-3001 (2022) - [j34]Qian Luo, Chunhe Yao, Ke Ning, Xuemin Zheng, Mingxin Zhao, Li Cheng, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu:
A Programmable and Flexible Vision Processor. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3884-3888 (2022) - [j33]Mingxin Zhao, Junbo Peng, Shuangming Yu, Liyuan Liu, Nanjian Wu:
Exploring Structural Sparsity in CNN via Selective Penalty. IEEE Trans. Circuits Syst. Video Technol. 32(3): 1658-1666 (2022) - [c50]Leyi Chen, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Cong Shi, Min Tian:
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. APCCAS 2022: 1-5 - [c49]Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, Nan Qi:
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. APCCAS 2022: 360-363 - [c48]Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang:
A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. APCCAS 2022: 556-559 - [c47]Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang:
A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. APCCAS 2022: 569-573 - [c46]Tengxiao Wang, Haibing Wang, Junxian He, Zhengqing Zhong, Fang Tang, Xichuan Zhou, Shuangming Yu, Liyuan Liu, Nanjian Wu, Min Tian, Cong Shi:
MorphBungee: An Edge Neuromorphic Chip for High-Accuracy On-Chip Learning of Multiple-Layer Spiking Neural Networks. BioCAS 2022: 255-259 - [c45]Yunqi Yang, Ming Zhong, Qianli Ma, Ziyi Lin, Leliang Li, Guike Li, Liyuan Liu, Jian Liu, Nanjian Wu, Haikun Jia, Xinghui Liu, Nan Qi:
A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O. ICTA 2022: 1-2 - [c44]Haozhe Xu, Siyuan Wei, Nan Qi, Peng Wu, Jian Liu, Nanjian Wu, Liyuan Liu, Shuangming Yu:
Floorplanning and Power/Ground Network Design for A Programmable Vision Chip. ICTA 2022: 184-185 - 2021
- [j32]Tengxiao Wang, Cong Shi, Xichuan Zhou, Yingcheng Lin, Junxian He, Ping Gan, Ping Li, Ying Wang, Liyuan Liu, Nanjian Wu, Gang Luo:
CompSNN: A lightweight spiking neural network based on spatiotemporally compressive spike features. Neurocomputing 425: 96-106 (2021) - [j31]Shuyu Wang, Mingxin Zhao, Runjiang Dou, Shuangming Yu, Liyuan Liu, Nanjian Wu:
A Compact High-Quality Image Demosaicking Neural Network for Edge-Computing Devices. Sensors 21(9): 3265 (2021) - [j30]Ling Zhang, Jing Yang, Cong Shi, Yingcheng Lin, Wei He, Xichuan Zhou, Xu Yang, Liyuan Liu, Nanjian Wu:
A Cost-Efficient High-Speed VLSI Architecture for Spiking Convolutional Neural Network Inference Using Time-Step Binary Spike Maps. Sensors 21(18): 6006 (2021) - [j29]Wei He, Jie Zhang, Yingcheng Lin, Xichuan Zhou, Ping Li, Liyuan Liu, Nanjian Wu, Cong Shi:
A Low-Cost High-Speed Object Tracking VLSI System Based on Unified Textural and Dynamic Compressive Features. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 1013-1017 (2021) - [j28]Cong Shi, Tengxiao Wang, Junxian He, Jianghao Zhang, Liyuan Liu, Nanjian Wu:
DeepTempo: A Hardware-Friendly Direct Feedback Alignment Multi-Layer Tempotron Learning Rule for Deep Spiking Neural Networks. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1581-1585 (2021) - [c43]Donglai Lu, Jian He, Weizhong Li, Sikai Chen, Jian Liu, Nanjian Wu, Ningmei Yu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi:
100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. APCCAS 2021: 253-256 - [c42]Peng Feng, Liyuan Liu, Nanjian Wu:
Pixel Design of Ultra-high Speed CMOS Image Sensor. ASICON 2021: 1-4 - [c41]Qiwen Liao, Miaofeng Li, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Nan Qi:
A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. CICC 2021: 1-2 - [c40]Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Liyuan Liu, Nanjian Wu, Cong Shi:
A Pixel-Parallel Array Processor without Computational Logic for Computational Image Sensors. ICTA 2021: 51-52 - [c39]Haibing Wang, Zhen He, Jinsong Rao, Tengxiao Wang, Junxian He, Min Tian, Xichuan Zhou, Liyuan Liu, Nanjian Wu, Cong Shi:
TripleBrain: An Edge Neuromorphic Architecture for High-accuracy Single-layer Spiking Neural Network with On-chip Self-organizing and Reinforcement Learning. ICTA 2021: 88-89 - [c38]Han Liu, Guike Li, Jian Liu, Nanjian Wu, Liyuan Liu, Yingtao Li, Nan Qi:
A Fast-Transient Capacitor-Less Low-Dropout Regulator for Wideband Optical Transceivers. ICTA 2021: 257-258 - [c37]Tong Fang, Min Liu, Liyuan Liu, Ziteng Cai, Runjiang Dou, Peng Feng, Nan Qi, Zhao Zhang, Jian Liu, Nanjian Wu:
A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. ICTA 2021: 259-260 - 2020
- [j27]Xu Yang, Zhongxing Zhang, Wenping Zhu, Shuangming Yu, Liyuan Liu, Nanjian Wu:
Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks. Sci. China Inf. Sci. 63(2): 122402 (2020) - [j26]Song Ma, Liyuan Liu, Tong Fang, Jian Liu, Nanjian Wu:
A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques. IEEE J. Solid State Circuits 55(2): 333-343 (2020) - [j25]Qiwen Liao, Nan Qi, Miaofeng Li, Shang Hu, Jian He, Bozhi Yin, Jingbo Shi, Jian Liu, Patrick Yin Chiang, Xi Xiao, Nanjian Wu:
A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS. IEEE J. Solid State Circuits 55(5): 1282-1296 (2020) - [j24]Wei He, Jinguo Huang, Tengxiao Wang, Yingcheng Lin, Junxian He, Xichuan Zhou, Ping Li, Ying Wang, Nanjian Wu, Cong Shi:
A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification. Sensors 20(17): 4715 (2020) - [j23]Mingxin Zhao, Ke Ning, Shuangming Yu, Liyuan Liu, Nanjian Wu:
Quantizing Oriented Object Detection Network via Outlier-Aware Quantization and IoU Approximation. IEEE Signal Process. Lett. 27: 1914-1918 (2020) - [c36]Yingcheng Lin, Rui Li, Wei He, Xichuan Zhou, Junxian He, Ping Li, Ying Jiang, Liyuan Liu, Nanjian Wu, Cong Shi:
A High-speed Low-cost CNN Inference Accelerator for Depthwise Separable Convolution. ICTA 2020: 63-64 - [c35]Hongtao Zhou, Runjiang Dou, Shuangming Yu, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu:
A High-Speed Parallel FPGA Implementation of Harris Corner Detection. ICTA 2020: 71-72 - [c34]Zhenhua Guo, Chao Gu, Shuangming Yu, Liyuan Liu, Jian Liu, Peng Feng, Nanjian Wu:
A Compact On-chip Analog Memory Cell for Storing TOF Image Signal in CMOS Process. ICTA 2020: 83-84 - [c33]Kai Hao, Jian He, Leliang Li, Shuangming Yu, Liyuan Liu, Jian Liu, Ningmei Yu, Nanjian Wu, Nan Qi:
A 28GBaud High-Swing Linear Mach-Zehnder Modulators Driver for PAM-4 and Coherent Optical Communications. ICTA 2020: 94-95 - [c32]Chao Gu, Zhenhua Guo, Shuangming Yu, Liyuan Liu, Jian Liu, Peng Feng, Nanjian Wu:
A Method of Estimating FD Capacitance with Large Size Photodiode in High Speed Imaging (Invited Paper). ICTA 2020: 141-142 - [c31]Yang Liu, Nan Qi, Xiuli Xu, Weizhong Li, Lei Wang, Minjia Chen, Qixiang Cheng, Jingbo Shi, Liyuan Liu, Jian Liu, Xi Xiao, Nanjian Wu:
A 50Gb/s PAM-4 Optical Receiver with Si-Photonic PD and Linear TIA in 40nm CMOS. ISCAS 2020: 1-4 - [c30]Mingxin Zhao, Xuemin Zheng, Ke Ning, Chunhe Yao, Qian Luo, Shuangming Yu, Liyuan Liu, Nanjian Wu:
A verification method for array-based vision chip using a fixed-point neural network simulation tool. LASCAS 2020: 1-4 - [i1]Mingxin Zhao, Li Cheng, Xu Yang, Peng Feng, Liyuan Liu, Nanjian Wu:
TBC-Net: A real-time detector for infrared small target detection using semantic constraint. CoRR abs/2001.05852 (2020)
2010 – 2019
- 2019
- [j22]Jincheng Yang, Zhao Zhang, Nan Qi, Liyuan Liu, Jian Liu, Nanjian Wu:
A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. Sci. China Inf. Sci. 62(6): 62405:1-62405:16 (2019) - [j21]Jiaqing Wang, Yongxing Yang, Liyuan Liu, Nanjian Wu:
High-speed target tracking system based on multi-interconnection heterogeneous processor and multi-descriptor algorithm. Sci. China Inf. Sci. 62(6): 69401:1-69401:3 (2019) - [j20]Qian Di, Zhongxing Zhang, Honglong Li, Zhao Zhang, Peng Feng, Nanjian Wu:
Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. IEICE Electron. Express 16(21): 20190544 (2019) - [j19]Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu:
0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. IET Circuits Devices Syst. 13(7): 1071-1077 (2019) - [j18]Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu:
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3733-3746 (2019) - [c29]Song Ma, Liyuan Liu, Jian Liu, Nanjian Wu:
A 8-b 1GS/s 2b/cycle SAR ADC in 28-nm CMOS. APCCAS 2019: 21-24 - [c28]Junxian He, Xichuan Zhou, Yingcheng Lin, Chonglei Sun, Cong Shi, Nanjian Wu, Gang Luo:
20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip. ASICON 2019: 1-4 - [c27]Jinguo Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, Nanjian Wu, Gang Luo:
High-speed Classification of AER Data Based on a Low-cost Hardware System. ASICON 2019: 1-4 - [c26]Nan Qi, Nanjian Wu:
Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS. ASICON 2019: 1-4 - [c25]Xu Yang, Shuangming Yu, Liyuan Liu, Jian Liu, Nanjian Wu:
Efficient Reservoir Encoding Method for Near-Sensor Classification with Rate-Coding Based Spiking Convolutional Neural Networks. ISNN (2) 2019: 242-251 - 2018
- [j17]Nanjian Wu:
Neuromorphic vision chips. Sci. China Inf. Sci. 61(6): 060421:1-060421:17 (2018) - [j16]Jie Yang, Yongxing Yang, Zhe Chen, Liyuan Liu, Jian Liu, Nanjian Wu:
A Heterogeneous Parallel Processor for High-Speed Vision Chip. IEEE Trans. Circuits Syst. Video Technol. 28(3): 746-758 (2018) - [j15]Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 933-944 (2018) - [c24]Tong Fang, Runjiang Dou, Liyuan Liu, Jian Liu, Nanjian Wu:
A 25 fps 32 × 24 Digital CMOS Terahertz Image Sensor. A-SSCC 2018: 87-90 - [c23]Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu:
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. A-SSCC 2018: 227-230 - 2017
- [j14]Yongxing Yang, Jie Yang, Zhongxing Zhang, Liyuan Liu, Nanjian Wu:
High-speed visual target tracking with mixed rotation invariant description and skipping searching. Sci. China Inf. Sci. 60(6): 62401 (2017) - [j13]Zhao-yang Liu, Liyuan Liu, Zhao Zhang, Jian Liu, Nanjian Wu:
Terahertz detector for imaging in 180-nm standard CMOS process. Sci. China Inf. Sci. 60(8): 82401 (2017) - [j12]Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter. IEICE Electron. Express 14(11): 20170422 (2017) - [j11]Yongxing Yang, Jie Yang, Liyuan Liu, Nanjian Wu:
High-Speed Target Tracking System Based on a Hierarchical Parallel Vision Processor and Gray-Level LBP Algorithm. IEEE Trans. Syst. Man Cybern. Syst. 47(6): 950-964 (2017) - [j10]Zhao Zhang, Liyuan Liu, Peng Feng, Nanjian Wu:
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 929-941 (2017) - [c22]Tong Fang, Zhao-yang Liu, Liyuan Liu, Yuan-Yuan Li, Jun-qi Liu, Jian Liu, Nanjian Wu:
Detection of 3.0 THz wave with a detector in 65 nm standard CMOS process. A-SSCC 2017: 189-192 - [c21]Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu:
A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique. A-SSCC 2017: 249-252 - [c20]Bing Xia, Nan Qi, Liyuan Liu, Nanjian Wu:
A low-power 2.4GHz ZigBee transceiver with inductor-less RF front-end for IoT applications. MWSCAS 2017: 1332-1335 - 2016
- [j9]Zhe Chen, Shan Di, Zhongxiang Cao, Qi Qin, Fei Ji, Liyuan Liu, Nanjian Wu:
A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure. Sci. China Inf. Sci. 59(4): 042409:1-042409:10 (2016) - [c19]Beichen Zhang, Runjiang Dou, Liyuan Liu, Nanjian Wu:
A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator. A-SSCC 2016: 317-320 - 2015
- [j8]Yangfan Zhou, Zhongxiang Cao, Ye Han, Quanliang Li, Cong Shi, Runjiang Dou, Qi Qin, Jian Liu, Nanjian Wu:
A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor. Sci. China Inf. Sci. 58(4): 1-10 (2015) - [c18]Honglong Li, Zhongxing Zhang, Jie Yang, Liyuan Liu, Nanjian Wu:
A novel vision chip architecture for image recognition based on convolutional neural network. ASICON 2015: 1-4 - [c17]Victor Nshunguyimfura, Jie Yang, Liyuan Liu, Nanjian Wu:
An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors. ASICON 2015: 1-4 - [c16]Jincheng Yang, Zhao Zhang, Peng Feng, Liyuan Liu, Nanjian Wu:
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. ASICON 2015: 1-4 - [c15]Zhongxing Zhang, Jie Yang, Honglong Li, Liyuan Liu, Jian Liu, Nanjian Wu:
High-speed object detection based on a hierarchical parallel vision chip. ASICON 2015: 1-4 - [c14]Zhao-yang Liu, Liyuan Liu, Jie Yang, Nanjian Wu:
A fully-integrated 860-GHz CMOS terahertz sensor. A-SSCC 2015: 1-4 - 2014
- [j7]Yangfan Zhou, Zhongxiang Cao, Qi Qin, Quanliang Li, Cong Shi, Nanjian Wu:
A high speed 1000 fps CMOS image sensor with low noise global shutter pixels. Sci. China Inf. Sci. 57(4): 1-8 (2014) - [j6]Cong Shi, Jie Yang, Nanjian Wu, ZhiHua Wang:
A high speed multi-level-parallel array processor for vision chips. Sci. China Inf. Sci. 57(6): 1-12 (2014) - [j5]Weiyang Liu, Jingjing Chen, Xiaodong Liu, Haiyong Wang, Nanjian Wu:
A 2.4 GHz low power CMOS transceiver for LR-WPAN applications. Sci. China Inf. Sci. 57(8): 1-13 (2014) - [j4]Cong Shi, Jie Yang, Liyuan Liu, Nanjian Wu, ZhiHua Wang:
A massively parallel keypoint detection and description (MP-KDD) algorithm for high-speed vision chip. Sci. China Inf. Sci. 57(10): 1-12 (2014) - [j3]Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang:
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network. IEEE J. Solid State Circuits 49(9): 2067-2082 (2014) - [c13]Zhao Zhang, Liyuan Liu, Nanjian Wu:
A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing. A-SSCC 2014: 369-372 - [c12]Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang:
7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. ISSCC 2014: 128-129 - 2013
- [j2]Weiyang Liu, Jingjing Chen, Haiyong Wang, Nanjian Wu:
A Low Power 2.4 GHz RF Transceiver for ZigBee Applications. J. Circuits Syst. Comput. 22(9) (2013) - [c11]Zhe Chen, Jie Yang, Cong Shi, Nanjian Wu:
A novel architecture of local memory for programmable SIMD vision chip. ASICON 2013: 1-4 - [c10]Jingjing Chen, Weiyang Liu, Peng Feng, Haiyong Wang, Nanjian Wu:
A 2.4 GHz energy-efficient 18-Mbps FSK transmitter in 0.18 μm CMOS. CICC 2013: 1-4 - 2012
- [c9]Nanjian Wu, Qi Zhang:
Ultra-low-power RF transceivers for WBANs in medical applications. NEWCAS 2012: 145-148 - 2011
- [j1]Qi Zhang, Peng Feng, Zhiqing Geng, Xiaozhou Yan, Nanjian Wu:
A 2.4-GHz Energy-Efficient Transmitter for Wireless Medical Applications. IEEE Trans. Biomed. Circuits Syst. 5(1): 39-47 (2011) - [c8]Yangfan Zhou, Zhongxiang Cao, Quanliang Li, Qi Qin, Nanjian Wu:
Design of four-transistor Pixel for high speed CMOS image. ASICON 2011: 171-174 - 2010
- [c7]Qi Zhang, Peng Feng, Shenghua Zhou, Zhiqing Geng, Nanjian Wu:
A novel RFID tag chip with temperature sensor in standard CMOS process. ISCAS 2010: 1109-1112
2000 – 2009
- 2009
- [c6]Xiaozhou Yan, Xiaofei Kuang, Nanjian Wu:
An accurate and fast behavioral model for PLL Frequency Synthesizer phase noise/spurs prediction. CICC 2009: 223-226 - [c5]Peng Feng, Yunlong Li, Nanjian Wu:
An ultra low power non-volatile memory in standard CMOS process for passive RFID tags. CICC 2009: 713-716 - [c4]Xiaozhou Yan, Xiaofei Kuang, Nanjian Wu:
A Smart Frequency Presetting Technique for Fast Lock-in LC-PLL Frequency Synthesizer. ISCAS 2009: 1525-1528 - 2007
- [c3]Haiyong Wang, Guoliang Shou, Nanjian Wu:
A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiver. ISCAS 2007: 3912-3915 - 2006
- [c2]Haiyong Wang, Guoliang Shou, Nanjian Wu:
An adaptive frequency synthesizer architecture reducing reference sidebands. ISCAS 2006 - [c1]Xiaofei Kuang, Nanjian Wu:
A fast-settling PLL frequency synthesizer with direct frequency presetting. ISSCC 2006: 741-750
Coauthor Index
[j54] [j53] [j52] [j51] [j50] [c66] [c65] [j46] [j45] [j44] [c63] [c62] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [j43] [j40] [j39] [j35] [j34] [c49] [c48] [c47] [c45] [c44] [c43] [c41] [c38] [c37] [j26] [j25] [c35] [c34] [c33] [c32] [c31] [j22] [j19] [j18] [c29] [c25] [j16] [j15] [c24] [c23] [j13] [j12] [c22] [c21] [j8] [c15]
[j53] [j52] [j51] [j50] [j49] [c66] [j47] [j46] [j45] [j44] [c64] [c63] [c62] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [j43] [j42] [j41] [j39] [j38] [j37] [j36] [j34] [j33] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [j32] [j31] [j30] [j29] [j28] [c43] [c42] [c40] [c39] [c38] [c37] [j27] [j26] [j23] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [i1] [j22] [j21] [j19] [j18] [c29] [c25] [j16] [j15] [c24] [c23] [j14] [j13] [j12] [j11] [j10] [c22] [c21] [c20] [j9] [c19] [c18] [c17] [c16] [c15] [c14] [j4] [j3] [c13] [c12]
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-23 20:30 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
