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Eric Fluhr
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2020 – today
- 2023
- [j7]Brian T. Vanderpool, Phillip J. Restle, Eric Fluhr, Gregory S. Still, Francesco A. Campisano, Ian Charmichael, Eric Marz, Rahul Batra, Richard L. Willaman:
Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. IEEE J. Solid State Circuits 58(1): 102-110 (2023) - 2022
- [c16]Brian T. Vanderpool, Phillip J. Restle, Eric J. Fluhr, Gregory S. Still, Frank Campisano, Ian Carmichael, Eric Marz, Rahul Batra, Richard L. Willaman:
Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. ISSCC 2022: 1-3 - [c15]Rahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse:
POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. ISSCC 2022: 48-50
2010 – 2019
- 2018
- [j6]Eric J. Fluhr, Rahul M. Rao, Howard Smith, Alper Buyuktosunoglu, Ramon Bertran Monfort:
IBM POWER9 circuit design and energy optimization for 14-nm technology. IBM J. Res. Dev. 62(4/5): 4:1-4:11 (2018) - [j5]Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench:
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits 53(1): 91-101 (2018) - 2017
- [c14]Philipp Salz, A. Frisch, Wolfgang Penth, J. Noack, T. Kalla, Rolf Sautter, Michael Kugel, Otto A. Torreiter, G. Sapp, Mike Lee, Eric Fluhr, A. Rozenfeld, Jürgen Pille, Dieter F. Wendel:
A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology. ESSCIRC 2017: 303-307 - [c13]Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass:
3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. ISSCC 2017: 50-51 - [c12]Michael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis:
26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. ISSCC 2017: 444-445 - 2016
- [c11]Eric Fluhr, Bing Sheu:
Session 8 overview: Low-power digital circuits. ISSCC 2016: 144-145 - [c10]Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma:
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. VLSID 2016: 493-498 - 2015
- [j4]Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny:
IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. 59(1) (2015) - [j3]Eric J. Fluhr, Steve Baumgartner, David W. Boerstler, John F. Bulzacchelli, Timothy Diemoz, Daniel Dreps, George English, Joshua Friedrich, Anne Gattiker, Tilman Gloekler, Christopher J. Gonzalez, Jason Hibbeler, Keith A. Jenkins, Yong Kim, Paul Muench, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Phillip J. Restle, Raphael Robertazzi, David Shan, David W. Siljenberg, Michael A. Sperling, Kevin Stawiasz, Gregory S. Still, Zeynep Toprak Deniz, James D. Warnock, Glen A. Wiedemeier, Victor V. Zyuban:
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. IEEE J. Solid State Circuits 50(1): 10-23 (2015) - [c9]Ken Chang, Frank O'Mahony, Elad Alon, Hyeon-Min Bae, Nicola Da Dalt, Eric Fluhr:
F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. ISSCC 2015: 1-2 - [c8]Mozammel Hossain, Eric Fluhr, Allen Hall, Vikas Agarwal:
Physical design and implementation of POWER8™ (P8) server class processor. MWSCAS 2015: 1-4 - 2014
- [c7]Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban:
POWER8 design methodology innovations for improving productivity and reducing power. CICC 2014: 1-9 - [c6]Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor:
The POWER8TM processor: Designed for big data, analytics, and cloud environments. ICICDT 2014: 1-4 - [c5]Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler:
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. ISSCC 2014: 96-97 - [c4]Eric Fluhr, Michael Polley, Se-Hyun Yang, Vasantha Erraguntla, Tobias Noll, Kees van Berkel:
F3: Adaptive design techniques for energy efficiency. ISSCC 2014: 514-515 - 2013
- [c3]Se-Hyun Yang, Eric Fluhr:
Session 3 overview: Processors. ISSCC 2013: 44-45
2000 – 2009
- 2008
- [j2]Benjamin Stolt, Yonatan Mittlefehldt, Sanjay Dubey, Gaurav Mittal, Mike Lee, Joshua Friedrich, Eric Fluhr:
Design and Implementation of the POWER6 Microprocessor. IEEE J. Solid State Circuits 43(1): 21-28 (2008) - 2007
- [j1]Brian W. Curran, Eric Fluhr, Jose Paredes, Leon J. Sigal, Joshua Friedrich, Yiu-Hing Chan, Charlie Hwang:
Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. IBM J. Res. Dev. 51(6): 715-732 (2007) - [c2]Joshua Friedrich, Bradley D. McCredie, Norman K. James, Bill Huott, Brian W. Curran, Eric Fluhr, Gaurav Mittal, Eddie Chan, Yuen H. Chan, Donald W. Plass, Sam G. Chu, Hung Q. Le, Leo Clark, John R. Ripley, Scott A. Taylor, Jack DiLullo, Mary Yvonne Lanzerotti:
Design of the Power6 Microprocessor. ISSCC 2007: 96-97 - 2006
- [c1]John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC 2006: 2564-2571
Coauthor Index
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