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ORCIDSachin B. Patkar
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2020 – today
- 2024
[c40]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC 2024: 282-287- [c39]Dhruva S. Hegde, Mandar Dalai, Manish Prajapati, Sachin B. Patkar, Gaurav Trivedi:
Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow. VDAT 2024: 1-6 - [c38]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. VLSI-SoC 2024: 1-6 - [c37]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger
, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID 2024: 565-570 - [i14]Mandar Datar, Dhruva S. Hegde, Vendra Durga Prasad, Manish Prajapati, Neralla Manikanta, Devansh Gupta, Janampalli Pavanija, Pratyush Pare, Akash, Shivam Gupta, Sachin B. Patkar:
Python-based DSL for generating Verilog model of Synchronous Digital Circuits. CoRR abs/2406.09208 (2024) - [i13]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. CoRR abs/2407.02921 (2024) - [i12]Simranjeet Singh, Farhad Merchant, Sachin B. Patkar:
Resistive Memory for Computing and Security: Algorithms, Architectures, and Platforms. CoRR abs/2407.03843 (2024) - 2023
- [j13]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15(4): 230-233 (2023) - [j12]Niraj N. Sharma, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant:
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. J. Syst. Archit. 135: 102801 (2023) - [c36]Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant:
Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. ASP-DAC 2023: 449-454 - [c35]Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik:
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. ISLPED 2023: 1-6 - [c34]Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant:
Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. NANOARCH 2023: 30:1-30:7 - [c33]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS 2023: 1-5 - [c32]Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant:
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. NEWCAS 2023: 1-5 - [i11]Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Vikas Rana, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant:
Integrated Architecture for Neural Networks and Security Primitives using RRAM Crossbar. CoRR abs/2304.13531 (2023) - [i10]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR abs/2304.13552 (2023) - [i9]Omar Ghazal, Simranjeet Singh, Tousif Rahman, Shengqi Yu, Yujin Zheng, Domenico Balsamo, Sachin B. Patkar, Farhad Merchant, Fei Xia, Alex Yakovlev, Rishad A. Shafik:
IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines. CoRR abs/2305.12914 (2023) - [i8]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR abs/2307.03669 (2023) - [i7]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR abs/2309.04868 (2023) - [i6]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR abs/2310.10460 (2023) - 2022
- [c31]Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant:
PA-PUF: A Novel Priority Arbiter PUF. VLSI-SoC 2022: 1-6 - [i5]Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant:
PA-PUF: A Novel Priority Arbiter PUF. CoRR abs/2207.10526 (2022) - [i4]Simranjeet Singh, Furqan Zahoor, Gokulnath Rajendran, Sachin B. Patkar, Anupam Chattopadhyay, Farhad Merchant:
Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs. CoRR abs/2211.03526 (2022) - 2020
- [j11]Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar:
Scalable implementation of particle filter-based visual object tracking on network-on-chip (NoC). J. Real Time Image Process. 17(5): 1117-1134 (2020) - [c30]Imran A. Syed, Mandar Datar, Sachin B. Patkar:
Accelerated Stereo Vision Using Nvidia Jetson and Intel AVX. CVIP (2) 2020: 137-148 - [c29]Yashwant Temburu, Mandar Datar, Simranjeet Singh, Vaibhav Malviya, Sachin B. Patkar:
Real time System Implementation for Stereo 3D Mapping and Visual Odometry. IPAS 2020: 7-13 - [c28]Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar:
FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation. VLSID 2020: 131-136 - [i3]Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers:
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. CoRR abs/2006.00364 (2020) - [i2]Prathmesh Sawant, Yashwant Temburu, Mandar Datar, Imran Ahmed, Vinayak Shriniwas, Sachin B. Patkar:
Single Storage Semi-Global Matching for Real Time Depth Processing. CoRR abs/2007.03269 (2020)
2010 – 2019
- 2019
- [c27]Shreeniwas N. Sapre, Sachin B. Patkar, Supratim Biswas:
Computational Issues in Construction of 4-D Projective Spaces with Perfect Access Patterns for Higher Primes. PaCT 2019: 245-259 - 2018
- [c26]Vinay B. Y. Kumar, Deval Shah, Mandar Datar, Sachin B. Patkar:
Lightweight Forth Programmable NoCs. VLSID 2018: 368-373 - 2016
- [c25]Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, H. Narayanan, Sachin B. Patkar:
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. VLSID 2016: 409-414 - 2015
- [c24]Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar:
Parallel two step random walk algorithm to analyze VLSI power grid networks. VDAT 2015: 1-2 - [c23]Pinalkumar Engineer, Rajbabu Velmurugan, Sachin B. Patkar:
Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video. VLSID 2015: 35-40 - [i1]Vinay B. Y. Kumar, Pinalkumar Engineer, Mandar Datar, Yatish Turakhia, Saurabh Agarwal, Sanket Diwale, Sachin B. Patkar:
Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies. CoRR abs/1508.06823 (2015) - 2014
- [c22]Vinay B. Y. Kumar, Shovan Maity, Sachin B. Patkar:
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping. ICCD 2014: 464-469 - [c21]Vivek Kumar, Vinay B. Y. Kumar, Sachin B. Patkar:
FPGA-based implementation of M4RM for matrix multiplication over GF(2). VDAT 2014: 1-2 - [c20]Janak Porwal, Sanket Diwale, Vinay B. Y. Kumar, Sachin B. Patkar:
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems. VLSI-DAT 2014: 1-4 - 2013
- [j10]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Solution of PDEs-electrically coupled systems with electrical analogy. Integr. 46(4): 427-440 (2013) - [c19]Prateek Saxena, Vinay B. Y. Kumar, Dilawar Singh, H. Narayanan, Sachin B. Patkar:
Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields. PECCS 2013: 195-201 - [c18]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Memory Efficient Implementation of Two Graph Based Circuit Simulator for PDE-Electrical Analogy. VLSI Design 2013: 356-361 - 2012
- [c17]Sumeet Agrawal, Pinal Engineer, Rajbabu Velmurugan, Sachin B. Patkar:
FPGA Implementation of Particle Filter Based Object Tracking in Video. ISED 2012: 82-86 - [c16]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Two Graph Based Circuit Simulator for PDE-Electrical Analogy. VLSI Design 2012: 400-405 - 2011
- [j9]Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Solution of Partial Differential Equations by electrical analogy. J. Comput. Sci. 2(1): 18-30 (2011) - [c15]Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik, Sachin B. Patkar:
Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA. PECCS 2011: 476-484 - 2010
- [j8]Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. Int. J. Parallel Program. 38(3-4): 322-338 (2010) - [c14]Subhendu Roy, Yogesh Dilip Save, H. Narayanan, Sachin B. Patkar:
Large Scale VLSI Circuit Simulation Using Point Relaxation. CSC 2010: 343-347
2000 – 2009
- 2009
- [c13]Anirudh Maringanti, Viraj Athavale, Sachin B. Patkar:
Acceleration of conjugate gradient method for circuit simulation using CUDA. HiPC 2009: 438-444 - [c12]Dinesh Baviskar, Sachin B. Patkar:
A Pipelined Simulation Approach for Logic Emulation using Multi-FPGA Platforms. ISCAS 2009: 1141-1144 - [c11]V. Siva Sankar, H. Narayanan, Sachin B. Patkar:
Exploiting Hybrid Analysis in Solving Electrical Networks. VLSI Design 2009: 206-211 - [c10]Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
FPGA Based High Performance Double-Precision Matrix Multiplication. VLSI Design 2009: 341-346 - 2005
- [c9]Janak Porwal, Sachin B. Patkar:
Algorithms For Scheduling Of Data Transfer Across FPGAs In A Grid. ERSA 2005: 255-260 - 2003
- [j7]Madhav P. Desai, H. Narayanan, Sachin B. Patkar:
The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function. Discret. Appl. Math. 131(2): 299-310 (2003) - [j6]Sachin B. Patkar, H. Narayanan:
Improving graph partitions using submodular functions. Discret. Appl. Math. 131(2): 535-553 (2003) - [j5]Sachin B. Patkar, H. Narayanan:
Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and its Connections with Principal Partition. J. Comb. Optim. 7(1): 45-68 (2003) - [c8]Sachin B. Patkar, H. Narayanan:
An Efficient Practical Heuristic For Good Ratio-Cut Partitioning. VLSI Design 2003: 64-69 - 2001
- [j4]Satoru Fujishige, Sachin B. Patkar:
Realization of set functions as cut functions of graphs and hypergraphs. Discret. Math. 226(1-3): 199-210 (2001) - [j3]Sachin B. Patkar, H. Narayanan:
A note on optimal covering augmentation for graphic polymatroids. Inf. Process. Lett. 79(6): 285-290 (2001) - 2000
- [c7]Sachin B. Patkar, H. Narayanan:
Fast On-Line/Off-Line Algorithms for Optimal Reinforcement of a Network and Its Connections with Principal Partition. FSTTCS 2000: 94-105
1990 – 1999
- 1999
- [c6]C. R. Venugopal, S. S. S. P. Rao, Sachin B. Patkar:
Priority Scheduling in Parallel I/O Systems. PDPTA 1999: 2554-2560 - 1997
- [c5]Sachin B. Patkar, Shabbir H. Batterywala, M. Chandramouli, H. Narayanan:
A New Partitioning Strategy Based on Supermodular Functions. VLSI Design 1997: 32-37 - 1996
- [j2]H. Narayanan, Subir K. Roy, Sachin B. Patkar:
Approximation Algorithms for Min-k-Overlap Problems Using the Principal Lattice of Partitions Approach. J. Algorithms 21(2): 306-330 (1996) - 1994
- [j1]Sachin B. Patkar, Brigitte Servatius, K. V. Subrahmanyam:
Abstract and Generic Rigidity in the Plane. J. Comb. Theory B 62(1): 107-113 (1994) - [c4]H. Narayanan, Subir K. Roy, Sachin B. Patkar:
Approximation Algorithms for Min-k-overlap Problems Using the Principal Lattice of Partitions Approach. MFCS 1994: 525-535 - 1992
- [c3]Sachin B. Patkar, H. Narayanan:
Fast Sequential and Randomised Parallel Algorithms for Rigidity and approximate Min k-cut. FSTTCS 1992: 265-278 - [c2]Sachin B. Patkar, H. Narayanan:
Principal Lattice of Partition of submodular functions on Graphs: Fast algorithms for Principal Partition and Generic Rigidity. ISAAC 1992: 41-50 - 1991
- [c1]Sachin B. Patkar, H. Narayanan:
A Fast Algorithm for the Principle Partition of a Graph. FSTTCS 1991: 288-306
Coauthor Index
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