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ORCIDGaurav Trivedi
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2020 – today
- 2024
[j38]Raghuvendra Pratap Tripathi
, Virat Krishna, Manish Tiwari, Gaurav Trivedi, Amit Dhawan, Prashant Kumar:
Low complexity, high throughput, energy efficient, pipelined and reconfigurable ASIC realization architecture for multi-layer perceptron models. Neurocomputing 598: 128013 (2024)- [j37]Rushik Parmar, Khushil Yadav, Gauraangi Anand, Gaurav Trivedi:
An SNN-Inspired Area- and Power-Efficient VLSI Architecture of Myocardial Infarction Classifier for Wearable Devices. IEEE Trans. Circuits Syst. II Express Briefs 71(6): 3191-3195 (2024) - [j36]Meenali Janveja, Rushik Parmar, Srichandan Dash, Jan Pidanic, Gaurav Trivedi:
A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1672-1683 (2024) - [c55]Bipul Boro, Rushik Parmar, Ashvinikumar Dongre, Gaurav Trivedi:
Reprogrammable Time-Domain RRAM Based Vector Matrix Multiplier for In-Memory Computing. ISQED 2024: 1-8 - [i4]Jack Krolik, Herprit Mahal, Feroz Ahmad, Gaurav Trivedi, Bahador Saket:
Towards Leveraging Large Language Models for Automated Medical Q&A Evaluation. CoRR abs/2409.01941 (2024) - 2023
- [j35]Deepak Joshi, Satyabrata Dash, Sushanth Reddy, Rahul Manigilla, Gaurav Trivedi:
Multi-objective Hybrid Particle Swarm Optimization and its Application to Analog and RF Circuit Optimization. Circuits Syst. Signal Process. 42(8): 4443-4469 (2023) - [j34]Sushree Sila P. Goswami, Gaurav Trivedi:
FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box. IEEE Embed. Syst. Lett. 15(4): 238-241 (2023) - [j33]Naorem Yaipharenba Meitei, Krishna Lal Baishnab, Gaurav Trivedi:
Fast power density aware three-dimensional integrated circuit floorplanning for hard macroblocks using best operator combination genetic algorithm. Int. J. Circuit Theory Appl. 51(10): 4879-4896 (2023) - [j32]Bikram Paul, Tarun Kumar Yadav, Balbir Singh, Srinivasan Krishnaswamy, Gaurav Trivedi:
A Resource Efficient Software-Hardware Co-Design of Lattice-Based Homomorphic Encryption Scheme on the FPGA. IEEE Trans. Computers 72(5): 1247-1260 (2023) - [j31]Bikram Paul, Angana Nath, Srinivasan Krishnaswamy, Jan Pidanic, Zdenek Nemec, Gaurav Trivedi:
Tensor Based Multivariate Polynomial Modulo Multiplier for Cryptographic Applications. IEEE Trans. Computers 72(6): 1581-1594 (2023) - [j30]Ashvinikumar Dongre, Gaurav Trivedi:
RRAM-Based Energy Efficient Scalable Integrate and Fire Neuron With Built-In Reset Circuit. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 909-913 (2023) - [j29]Meenali Janveja, Rushik Parmar, Gaurav Trivedi:
MInSC: A VLSI Architecture for Myocardial Infarction Stages Classifier for Wearable Healthcare Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1159-1163 (2023) - [j28]Ananda Y. R., Gadipelli Sriharsha Satyanarayan, Gaurav Trivedi:
A High Frequency MOS-Based Floating Charge-Controlled Memcapacitor Emulator. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1189-1193 (2023) - [j27]Rushik Parmar, Meenali Janveja, Jan Pidanic, Gaurav Trivedi:
Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices. IEEE Trans. Very Large Scale Integr. Syst. 31(3): 320-330 (2023) - [j26]Ananda Y. R., Nehal Raj, Gaurav Trivedi:
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications. IEEE Trans. Very Large Scale Integr. Syst. 31(3): 355-368 (2023) - [j25]Meenali Janveja, Ashwani Kumar Sharma, Abhyuday Bhardwaj, Jan Pidanic, Gaurav Trivedi:
An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2008-2015 (2023) - [j24]Ashvinikumar Dongre, Bipul Boro, Gaurav Trivedi:
ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2053-2060 (2023) - [c54]Bipul Boro, Ashvinikumar Dongre, Rushik Parmar, Gaurav Trivedi:
Programmable Binary Weighted Time-Domain Vector Matrix Multiplier for In-Memory Computing. APCCAS 2023: 261-265 - [c53]Ashvinikumar Dongre, Gaurav Trivedi:
Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit. ISQED 2023: 1-6 - [c52]Ananda Y. R., Subhashis Das, Gaurav Trivedi:
A Novel Dynamic Memristor Window Function for High Frequency Applications. NEWCAS 2023: 1-5 - [c51]Sushree Sila P. Goswami, Gaurav Trivedi:
Comparison of Hardware Implementations of Cryptographic Algorithms for IoT Applications. RADIOELEKTRONIKA 2023: 1-6 - [c50]Ananda Y. R., Arkadeep Hajra, Gaurav Trivedi:
An Adaptive Window Function based Memristor Model. RADIOELEKTRONIKA 2023: 1-5 - [c49]Ankita Tiwari, Prithwijit Guha, Gaurav Trivedi, Nitesh Gupta, Navneeth Jayaraj, Jan Pidanic:
IndiRA: Design and Implementation of a Pipelined RISC-V Processor. RADIOELEKTRONIKA 2023: 1-6 - 2022
- [j23]Bikram Paul, Souradip Pal, Abhishek Agrawal, Gaurav Trivedi:
Triple Pendulum Based Nonlinear Chaos Generator and its Applications in Cryptography. IEEE Access 10: 127073-127093 (2022) - [j22]Sumit Agarwal, Shaik Rafi Ahamed, Anup Kumar Gogoi, Gaurav Trivedi:
A 28-Gbps Radix-16, 512-Point FFT Processor-Based Continuous Streaming OFDM for WiGig. Circuits Syst. Signal Process. 41(5): 2871-2897 (2022) - [j21]Tomás Krejcí, Tomás Zálabský, Dusan Kopecký, Gaurav Trivedi:
Application of hash function for generation of modulation data in RadCom system. Digit. Signal Process. 130: 103735 (2022) - [j20]Ananda Y. R., Gadipelli Sriharsha Satyanarayan, Gaurav Trivedi:
A Flux Controlled MOS-Based Optimized High Frequency Meminductor Emulator. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 774-784 (2022) - [j19]Ananda Y. R., Gadipelli Sriharsha Satyanarayan, Gaurav Trivedi:
An Optimized MOS-Based High Frequency Charge-Controlled Memcapacitor Emulator. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 793-803 (2022) - [j18]Meenali Janveja, Gaurav Trivedi:
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications. Integr. 82: 96-103 (2022) - [j17]Meenali Janveja, Rushik Parmar, Mayank Tantuway, Gaurav Trivedi:
A DNN-Based Low Power ECG Co-Processor Architecture to Classify Cardiac Arrhythmia for Wearable Devices. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2281-2285 (2022) - [c48]Meenali Janveja, Rushik Parmar, Gaurav Trivedi, Jan Pidanic, Zdenek Nemec:
An Energy Efficient and Resource Optimal VLSI Architecture for ECG Feature Extraction for Wearable Healthcare Applications. RADIOELEKTRONIKA 2022: 1-6 - [c47]Saras Mani Mishra, Hanumant Singh Shekhawat, Gaurav Trivedi, Jan Pidanic, Zdenek Nemec:
Design and Implementation of a Low Power Area Efficient Bfloat16 based CORDIC Processor. RADIOELEKTRONIKA 2022: 1-6 - [c46]Saras Mani Mishra, Ankita Tiwari, Hanumant Singh Shekhawat, Prithwijit Guha, Gaurav Trivedi, Jan Pidanic, Zdenek Nemec:
Comparison of Floating-point Representations for the Efficient Implementation of Machine Learning Algorithms. RADIOELEKTRONIKA 2022: 1-6 - [c45]Rushik Parmar, Meenali Janveja, Gaurav Trivedi, Jan Pidanic, Zdenek Nemec:
An Area and Power Efficient VLSI Architecture to Detect Obstructive Sleep Apnea for Wearable Devices. RADIOELEKTRONIKA 2022: 1-5 - [c44]Jan Pidanic, Arpan Vyas, Rishav Karki, Prateek Vij, Gaurav Trivedi, Zdenek Nemec:
A Scalable and Adaptive Convolutional Neural Network Accelerator. RADIOELEKTRONIKA 2022: 1-5 - [c43]Ankita Tiwari, Saras Mani Mishra, Prithwijit Guha, Jan Pidanic, Zdenek Nemec, Gaurav Trivedi:
Design of a Low Power and Area Efficient Bfloat16 based Generalized Systolic Array for DNN Applications. RADIOELEKTRONIKA 2022: 1-5 - 2021
- [j16]Sushanta Bordoloi, Ashok Ray, Gaurav Trivedi:
Introspection Into Reliability Aspects in AlGaN/GaN HEMTs With Gate Geometry Modification. IEEE Access 9: 99828-99841 (2021) - [j15]Sumit Agarwal, Shaik Rafi Ahamed, Anup Kumar Gogoi, Gaurav Trivedi:
A Low-Complexity Shifting-Based Conflict-Free Memory-Addressing Architecture for Higher-Radix FFT. IEEE Access 9: 140349-140357 (2021) - [j14]Sukanta Dey, Sukumar Nandi, Gaurav Trivedi:
PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique. Microprocess. Microsystems 81: 103440 (2021) - [c42]Sukanta Dey, Sukumar Nandi, Gaurav Trivedi:
Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design. ISVLSI 2021: 378-383 - [c41]Meenali Janveja, Mayank Tantuway, Ketan Chaudhari, Gaurav Trivedi:
Design of Low Power VLSI Architecture for Classification of Arrhythmic Beats Using DNN for Wearable Device Applications. NorCAS 2021: 1-6 - 2020
- [j13]Sarfraz Hussain, Rajesh Kumar, Gaurav Trivedi:
Methodology and comparative design of an efficient 4-bit encoder with bubble error corrector for 1-GSPS flash type ADC. IET Circuits Devices Syst. 14(5): 629-639 (2020) - [j12]Naorem Yaipharenba Meitei, Krishna Lal Baishnab, Gaurav Trivedi:
3D-IC partitioning method based on genetic algorithm. IET Circuits Devices Syst. 14(7): 1104-1109 (2020) - [j11]Sukanta Dey, Sukumar Nandi, Gaurav Trivedi:
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network. ACM Trans. Design Autom. Electr. Syst. 25(5): 42:1-42:29 (2020) - [c40]Sukanta Dey, Sukumar Nandi, Gaurav Trivedi:
PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning. DATE 2020: 1520-1525 - [c39]Shikhar Gupta, Arpan Vyas, Gaurav Trivedi:
FPGA Implementation of Simplified Spiking Neural Network. ICECS 2020: 1-4 - [c38]Krishna Mohan Dwivedi, Gaurav Trivedi, Sunil K. Khijwania:
Theoretical Study and Optimization of Apodized Fiber Bragg Grating for Single and Quasi-distributed Structural Health Monitoring Applications. RADIOELEKTRONIKA 2020: 1-6 - [c37]Sushree Sila P. Goswami, Bikram Paul, Sunil Dutt, Gaurav Trivedi:
Comparative Review of Approximate Multipliers. RADIOELEKTRONIKA 2020: 1-6 - [c36]Meenali Janveja, Bikram Paul, Gaurav Trivedi, Gonella Vijayakanthi, Astha Agrawal, Jan Pidanic, Zdenek Nemec:
Design of Efficient AES Architecture for Secure ECG Signal Transmission for Low-power IoT Applications. RADIOELEKTRONIKA 2020: 1-6 - [p2]Sukanta Dey, Sukumar Nandi, Gaurav Trivedi:
PGRDP: Reliability, Delay, and Power-Aware Area Minimization of Large-Scale VLSI Power Grid Network Using Cooperative Coevolution. Intelligent Computing Paradigm 2020: 69-84 - [i3]Sukanta Dey, Sukumar Nandi, Gaurav Trivedi:
PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning. CoRR abs/2005.01386 (2020) - [i2]Shikhar Gupta, Arpan Vyas, Gaurav Trivedi:
FPGA Implementation of Simplified Spiking Neural Network. CoRR abs/2010.01200 (2020)
2010 – 2019
- 2019
- [j10]Gaurav Trivedi, Esmaeel R. Dadashzadeh, Robert M. Handzel, Wendy W. Chapman, Shyam Visweswaran, Harry Hochheiser:
Interactive NLP in Clinical Care: Identifying Incidental Findings in Radiology Reports. Appl. Clin. Inform. 10(04): 655-669 (2019) - [j9]Gaurav Trivedi, Charmgil Hong, Esmaeel R. Dadashzadeh, Robert M. Handzel, Harry Hochheiser, Shyam Visweswaran:
Identifying incidental findings from radiology reports of trauma patients: An evaluation of automated feature representation methods. Int. J. Medical Informatics 129: 81-87 (2019) - [j8]Sunil Dutt, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi:
Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders. IEEE Trans. Computers 68(3): 314-330 (2019) - [c35]Ajeyo Dey, Satyabrata Dash, Likhita Tumati, Saumitra Sharma, Nikhil Megharajani, Meenali Janveja, Ismael Rodríguez, Gaurav Trivedi:
A Cooperative Co-evolution based Scalable Framework for Solving Large-Scale Global optimization Problems. SMC 2019: 1689-1694 - [c34]Satyabrata Dash, Gaurav Trivedi:
Convergence Analysis of River Formation Dynamics Algorithm. SMC 2019: 2053-2058 - [c33]Satyabrata Dash, Sukanta Dey, Anish Augustine, Sankar Dhar, Jan Pidanic, Zdenek Nemec, Gaurav Trivedi:
RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic. VLSID 2019: 233-238 - [c32]Koushik Bharadwaj, Ashok Ray, Sushanta Bordoloi, Gaurav Trivedi:
Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor. VLSID 2019: 494-495 - [c31]Bikram Paul, Apratim Khobragade, Soumith Javvaji Sai, Sushree Sila P. Goswami, Sunil Dutt, Gaurav Trivedi:
Design and Implementation of Low-Power High-throughput PRNGs for Security Applications. VLSID 2019: 535-536 - [p1]Satyabrata Dash, Deepak Joshi, Sukanta Dey, Meenali Janveja, Gaurav Trivedi:
StormOptimus: A Single Objective Constrained Optimizer Based on Brainstorming Process for VLSI Circuits. Brain Storm Optimization Algorithms 2019: 221-243 - 2018
- [j7]Sunil Dutt, Sukumar Nandi, Gaurav Trivedi:
Accuracy enhancement of equal segment based approximate adders. IET Comput. Digit. Tech. 12(5): 206-215 (2018) - [j6]Gaurav Trivedi, Phuong Pham, Wendy W. Chapman, Rebecca Hwa, Janyce Wiebe, Harry Hochheiser:
NLPReViz: an interactive tool for natural language processing on clinical text. J. Am. Medical Informatics Assoc. 25(1): 81-87 (2018) - [j5]Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi:
Kapees3: A High-Quality VLSI Placement Tool Using Nesterov's Method for Density Penalty. J. Circuits Syst. Comput. 27(8): 1850122:1-1850122:29 (2018) - [j4]Satyabrata Dash, Sukanta Dey, Deepak Joshi, Gaurav Trivedi:
Minimizing area of VLSI power distribution networks using river formation dynamics. J. Syst. Inf. Technol. 20(4): 417-429 (2018) - [j3]Satyabrata Dash, Deepak Joshi, Gaurav Trivedi:
Multiobjective analog/RF circuit sizing using an improved brain storm optimization algorithm. Memetic Comput. 10(4): 423-440 (2018) - [j2]Sunil Dutt, Sukumar Nandi, Gaurav Trivedi:
Analysis and Design of Adders for Approximate Computing. ACM Trans. Embed. Comput. Syst. 17(2): 40:1-40:28 (2018) - [c30]Gaurav Trivedi, Robert M. Handzel, Shyam Visweswaran, Wendy W. Chapman, Harry Hochheiser:
An Interactive NLP Tool for Signout Note Preparation. ICHI 2018: 426-428 - [c29]Gaurav Trivedi:
Towards Interactive Natural Language Processing in Clinical Care. ICHI 2018: 448-449 - [c28]Sukanta Dey, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi:
PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution. ISVLSI 2018: 40-45 - 2017
- [c27]Sarfraz Hussain, Rajesh Kumar, Gaurav Trivedi:
A Novel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology. iNIS 2017: 133-138 - [c26]Sarfraz Hussain, Rajesh Kumar, Gaurav Trivedi:
Comparison and Design of Dynamic Comparator in 180nm SCL Technology for Low Power and High Speed Flash ADC. iNIS 2017: 139-144 - [c25]Pankaj Kumar, Syed Samsuz Zaman, Manash Pratim Sarma, Ashok Ray, Gaurav Trivedi:
Basic CMOS Gate Design by Mixed-Mode Analysis of Step-Channel TMDG-MOSFET. iNIS 2017: 173-178 - [c24]Syed Samsuz Zaman, Pankaj Kumar, Manash Pratim Sarma, Ashok Ray, Gaurav Trivedi:
Design and Simulation of SF-FinFET and SD-FinFET and Their Performance in Analog, RF and Digital Applications. iNIS 2017: 200-205 - [c23]Sunil Dutt, Bikram Paul, Anshu Chauhan, Sukumar Nandi, Gaurav Trivedi:
Approxhash: delay, power and area optimized approximate hash functions for cryptography applications. SIN 2017: 291-294 - [c22]Ashok Ray, Gaurav Kumar, Sushanta Bordoloi, Dheeraj Kumar Sinha, Pratima Agarwal, Gaurav Trivedi:
FEM Based Device Simulator for High Voltage Devices. VDAT 2017: 127-135 - [c21]Sameer Pawanekar, Gaurav Trivedi:
Fast FPGA Placement Using Analytical Optimization. VDAT 2017: 681-693 - [c20]Sameer Pawanekar, Gaurav Trivedi:
Analytical Partitioning: Improvement over FM. VDAT 2017: 718-730 - [c19]Sukanta Dey, Satyabrata Dash, Sukumar Nandi, Gaurav Trivedi:
Markov Chain Model Using Lévy Flight for VLSI Power Grid Analysis. VLSID 2017: 107-112 - [c18]Deepak Joshi, Satyabrata Dash, Ayush Malhotra, Pulimi Venkata Sai, Rahul Das, Dikshit Sharma, Gaurav Trivedi:
Optimization of 2.4 GHz CMOS Low Noise Amplifier Using Hybrid Particle Swarm Optimization with Lévy Flight. VLSID 2017: 181-186 - [i1]Gaurav Trivedi, Phuong Pham, Wendy W. Chapman, Rebecca Hwa, Janyce Wiebe, Harry Hochheiser:
An Interactive Tool for Natural Language Processing on Clinical Text. CoRR abs/1707.01890 (2017) - 2016
- [c17]Sunil Dutt, Harsh Patel, Sukumar Nandi, Gaurav Trivedi:
Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications. VLSID 2016: 134-139 - [c16]Satyabrata Dash, Krishna Lal Baishnab, Gaurav Trivedi:
Applying River Formation Dynamics to Analyze VLSI Power Grid Networks. VLSID 2016: 258-263 - [c15]Dheeraj Kumar Sinha, Amitabh Chatterjee, Vishnuram Abhinav, Gaurav Trivedi, Victor Koldyaev:
A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET. VLSID 2016: 312-317 - 2015
- [c14]Gaurav Trivedi:
Clinical Text Analysis Using Interactive Natural Language Processing. IUI Companion 2015: 113-116 - [c13]Jaromír Savelka, Gaurav Trivedi, Kevin D. Ashley:
Applying an Interactive Machine Learning Approach to Statutory Analysis. JURIX 2015: 101-110 - [c12]Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar:
Parallel two step random walk algorithm to analyze VLSI power grid networks. VDAT 2015: 1-2 - [c11]Sameer Pawanekar, Gaurav Trivedi:
TSV aware standard cell placement for 3D ICs. VDAT 2015: 1-6 - [c10]Sameer Pawanekar, Gaurav Trivedi:
Net weighing based timing driven standard cell placer. VDAT 2015: 1-6 - [c9]Sunil Dutt, Anshu Chauhan, Sukumar Nandi, Gaurav Trivedi:
Variability-aware parametric yield enhancement via post-silicon tuning of hybrid redundant MAC units. VLSI-DAT 2015: 1-4 - [c8]Sunil Dutt, Anshu Chauhan, Rahul Bhadoriya, Sukumar Nandi, Gaurav Trivedi:
A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications. VLSID 2015: 351-356 - [c7]Sameer Pawanekar, Gaurav Trivedi, Kalpesh Kapoor:
A Nonlinear Analytical Optimization Method for Standard Cell Placement of VLSI Circuits. VLSID 2015: 423-428 - 2013
- [j1]Hemangee K. Kapoor, G. Bhoopal Rao, Sharique Arshi, Gaurav Trivedi:
A Security Framework for NoC Using Authenticated Encryption and Session Keys. Circuits Syst. Signal Process. 32(6): 2605-2622 (2013) - [c6]Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi:
Kapees: A New Tool for Standard Cell Placement. VDAT 2013: 66-73 - 2012
- [c5]Ranjitha Gurunath Kulkarni, Gaurav Trivedi, Tushar Suresh, Miaomiao Wen, Zeyu Zheng, Carolyn P. Rosé:
Supporting collaboration in Wikipedia between language communities. ICIC 2012: 47-56
2000 – 2009
- 2007
- [c4]Gaurav Trivedi, H. Narayanan:
Application of Fast DC Analysis to Partitioning Hypergraphs. ISCAS 2007: 3407-3410 - [c3]Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Parallelization of DC Analysis through Multiport Decomposition. VLSI Design 2007: 863-868 - [c2]Gaurav Trivedi, Sumit Punglia, H. Narayanan:
Application of DC Analyzer to Combinatorial Optimization Problems. VLSI Design 2007: 869-874 - 2006
- [c1]Gaurav Trivedi, Madhav P. Desai, H. Narayanan:
Fast DC Analysis and Its Application to Combinatorial Optimization Problems. VLSI Design 2006: 695-700
Coauthor Index
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