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2010 – 2019
- 2018
[j17]Yen-Long Lee
, Yu-Po Cheng, Soon-Jyh Chang, Hsin-Wen Ting:
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs. IEEE Des. Test 35(1): 63-73 (2018)- [j16]Hsin-Wen Ting, Chi-Yuan Chen:
A VLSI On-Chip Analog High-Order Low-Pass Filter Performance Evaluation Strategy. IEEE Trans. Instrum. Meas. 67(3): 621-633 (2018) - 2017
- [j15]I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting:
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 621-634 (2017) - [c5]Chi-Hsien Wu, Jau-Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu:
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology. ISOCC 2017: 276-277 - 2016
- [j14]Hsin-Wen Ting:
A Digital Testing Strategy for Characterizing an Analog Circuit Block. IEEE Trans. Instrum. Meas. 65(6): 1374-1384 (2016) - [j13]Chun-Po Huang, Hsin-Wen Ting, Soon-Jyh Chang:
Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs. IEEE Trans. Instrum. Meas. 65(8): 1804-1817 (2016) - 2015
- [j12]An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang:
A capacitance-ratio quantification design for linearity test in differential top-plate sampling sar ADCS. Int. J. Circuit Theory Appl. 43(10): 1333-1350 (2015) - 2014
- [j11]An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, Soon-Jyh Chang:
A Low-Cost Stimulus Design for Linearity Test in SAR ADCs. IEICE Trans. Electron. 97-C(6): 538-545 (2014) - 2012
- [j10]Hsin-Wen Ting:
Digital-Compatible Testing Scheme for Operational Amplifier. J. Electron. Test. 28(3): 267-277 (2012) - [j9]I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting:
A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing. IEICE Trans. Electron. 95-C(11): 1799-1809 (2012) - [j8]Ren-Li Chen, Hsin-Wen Ting, Soon-Jyh Chang:
Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers. IET Circuits Devices Syst. 6(2): 95-102 (2012) - 2011
- [j7]Hsin-Wen Ting, Soon-Jyh Chang, Su-Ling Huang:
A Design of Linearity Built-in Self-Test for Current-Steering DAC. J. Electron. Test. 27(1): 85-94 (2011) - [j6]Hsin-Wen Ting:
An Output Response Analyzer Circuit for ADC Built-in Self-Test. J. Electron. Test. 27(4): 455-464 (2011) - [j5]Jin-Fu Lin, Hsin-Wen Ting:
Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs. J. Electron. Test. 27(6): 697-709 (2011) - [j4]Hsieh-Wei Lee, King-Chu Hung, Bin-Da Liu, Sheau-Fang Lei, Hsin-Wen Ting:
Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1287-1299 (2011) - [j3]Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, Chih-Hao Huang:
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2158-2169 (2011) - [c4]An-Sheng Chao, Soon-Jyh Chang, Hsin-Wen Ting:
A SAR ADC BIST for simplified linearity test. SoCC 2011: 146-149
2000 – 2009
- 2008
- [j2]Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
A Histogram-Based Testing Method for Estimating A/D Converter Performance. IEEE Trans. Instrum. Meas. 57(2): 420-427 (2008) - 2007
- [j1]Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, Soon-Jyh Chang:
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST. J. Electron. Test. 23(6): 549-558 (2007) - 2006
- [c3]Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu:
A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. APCCAS 2006: 426-429 - [c2]Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
Histogram Based Testing Strategy for ADC. ATS 2006: 51-54 - 2004
- [c1]Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. Asian Test Symposium 2004: 52-57
Coauthor Index
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