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2020 – today
- 2023
[i1]Benjamin M. Ampel, Chi-Heng Yang, James Lee Hu, Hsinchun Chen:
Large Language Models for Conducting Advanced Text Analytics Information Systems Research. CoRR abs/2312.17278 (2023)- 2022
- [c5]Chi-Heng Yang, Ju-Chun Yen, Tawei David Wang:
Human vs machine: Do customer service chatbots perform better? PACIS 2022: 61
2010 – 2019
- 2017
- [c4]Wei Lin, Yu-Cheng Hsu, Tsai-Hao Kuo, Yu-Siang Yang, Szu-Wei Chen, Chun-Wei Tsao, An-Chang Liu, Lih-Yuarn Ou, Tien-Ching Wang, Shao-Wei Yen, Yu-Hsiang Lin, Kuo-Hsin Lai, Chi-Heng Yang, Li-Chun Liang, Pei-Jung Hsu:
3X endurance enhancement by advanced signal processor for 3D NAND flash memory. ITW 2017: 201-203 - 2015
- [j2]Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1235-1244 (2015) - 2013
- [c3]Chi-Heng Yang, Yi-Hsun Chen, Hsie-Chia Chang:
An area-efficient BCH codec with echelon scheduling for NAND flash applications. ICC 2013: 4332-4336 - 2012
- [c2]Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang:
A fully parallel BCH codec with double error correcting capability for NOR flash applications. ICASSP 2012: 1605-1608 - [c1]Yi-Hsun Chen, Chi-Heng Yang, Hsie-Chia Chang:
A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. VLSI-DAT 2012: 1-4 - 2011
- [j1]Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 682-686 (2011)
Coauthor Index
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