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2020 – today
- 2024
[j98]Hsi-Hao Huang
, Tzu-Yun Huang, Chun-Hsien Liu, Sheng-Di Lin, Chen-Yi Lee:
A Dual-Mode Readout Circuit for SPAD Imaging Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 1879-1883 (2024)- [j97]Tzu-Yun Huang, Po-Ya Huang, Chen-Yi Lee:
A Low-Latency Data Compressor for SPAD-Based Depth Estimation Systems. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2334-2338 (2024) - [c137]Wen-Yue Lin, Lin-Hung Lai, Yi-Wei Lin, Chen-Yi Lee:
A Programmable CMOS Dielectrophoresis Array Chip with 128 × 128 Electrodes for Cell Manipulation. ISCAS 2024: 1-5 - [c136]Heng-Yu Liu, Lin-Hung Lai, Wen-Yue Lin, Yu-Wei Lu, Yi-Wei Lin, Chen-Yi Lee:
A 2.56-µs Dynamic Range, 31.25-ps Resolution 2-D Vernier Digital-to-Time Converter (DTC) for Cell-Monitoring. ISCAS 2024: 1-5 - [c135]Yi-Cheng Yu, Cheng-Fu Liou, Shang-Wen Chuang, Chen-Yi Lee:
Industrial Semiconductor GPT: A Question-and-Answer System that Provides Professional Advice and Problem-Solving Methods for Semiconductor and Factory Equipment and Process. ISIE 2024: 1-6 - 2023
- [j96]Lin-Hung Lai, Wen-Yue Lin, Yu-Wei Lu, Heng-Yu Lui, Shinsuke Yoshida, Shih-Hwa Chiou, Chen-Yi Lee:
A 460 800 Pixels CMOS Capacitive Sensor Array With Programmable Fusion Pixels and Noise Canceling for Life Science Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1734-1738 (2023) - [c134]Yun-Sheng Chan, Jiajie Diao, Chen-Yi Lee:
A Pattern-Control Digital Microfluidic Bio-Chip for Fast Thermal Cycle in Nucleic Acid Amplification Tests. ISCAS 2023: 1-4 - [c133]Tzu-Yun Huang, Hsi-Hao Huang, Chun-Hsien Liu, Sheng-Di Lin, Chen-Yi Lee:
A Stack-Based In-Pixel Storage Circuit for SPAD Photon Counting. ISCAS 2023: 1-5 - [c132]Hsi-Hao Huang, Chun-Hsien Liu, Tzu-Yun Huang, Sheng-Di Lin, Chen-Yi Lee:
Self-Restoring and Low-Jitter Circuits for High Timing-Resolution SPAD Sensing Applications. ISCAS 2023: 1-5 - [c131]Eugene Lee, Lien-Feng Hsu, Evan Chen, Chen-Yi Lee:
Cross-Resolution Flow Propagation for Foveated Video Super-Resolution. WACV 2023: 1766-1775 - 2022
- [j95]Yun-Sheng Chan, Ting-Ting Hsu, Yi-Po Chen, Hsu-Min Wu, Yun-Ming Wang, Chen-Yi Lee:
A Traveling-Wave Dielectrophoresis Bio-Chip for Cell Manipulation in Standard CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1582-1586 (2022) - [j94]Yun-Sheng Chan, Chen-Yi Lee:
A Programmable Bio-Chip With Adaptive Pattern-Control Micro-Electrode-Dot-Array. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4513-4517 (2022) - [c130]Yi-Cheng Yu, Shang-Wen Chuang, Hong-Han Shuai, Chen-Yi Lee:
Fast Adaption for Multi Motor Anomaly Detection via Meta Learning and deep unsupervised learning. ISIE 2022: 1186-1189 - [c129]Chen-Yi Lee:
Bio-Chips for Fast Medial Tests Networks. VLSI-DAT 2022: 1 - [i4]Eugene Lee, Lien-Feng Hsu, Evan Chen, Chen-Yi Lee:
Cross-Resolution Flow Propagation for Foveated Video Super-Resolution. CoRR abs/2212.13525 (2022) - 2021
- [c128]Eugene Lee, Cheng-Han Huang, Chen-Yi Lee:
Few-Shot and Continual Learning with Attentive Independent Mechanisms. ICCV 2021: 9435-9444 - [i3]Eugene Lee, Cheng-Han Huang, Chen-Yi Lee:
Few-Shot and Continual Learning with Attentive Independent Mechanisms. CoRR abs/2107.14053 (2021) - 2020
- [j93]Kit Hwa Cheah, Humaira Nisar, Vooi Voon Yap, Chen-Yi Lee:
Convolutional neural networks for classification of music-listening EEG: comparing 1D convolutional kernels with 2D kernels and cerebral laterality of musical influence. Neural Comput. Appl. 32(13): 8867-8891 (2020) - [j92]Kuang-Yow Lian, Wei-Hsiu Hsu, Deepak Balram, Chen-Yi Lee:
A Real-Time Wearable Assist System for Upper Extremity Throwing Action Based on Accelerometers. Sensors 20(5): 1344 (2020) - [j91]Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee:
Multitarget Sample Preparation Using MEDA Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2682-2695 (2020) - [j90]Sheng Wan, Tung-Yu Wu, Heng-Wei Hsu, Wing Hung Wong, Chen-Yi Lee:
Feature Consistency Training With JPEG Compressed Images. IEEE Trans. Circuits Syst. Video Technol. 30(12): 4769-4780 (2020) - [j89]Hsiao-Chien Yang, Po-Heng Chen, Kuan-Wen Chen, Chen-Yi Lee, Yong-Sheng Chen:
FADE: Feature Aggregation for Depth Estimation With Multi-View Stereo. IEEE Trans. Image Process. 29: 6590-6600 (2020) - [c127]Eugene Lee, Chen-Yi Lee:
NeuralScale: Efficient Scaling of Neurons for Resource-Constrained Deep Neural Networks. CVPR 2020: 1475-1484 - [c126]Eugene Lee, Evan Chen, Chen-Yi Lee:
Meta-rPPG: Remote Heart Rate Estimation Using a Transductive Meta-learner. ECCV (27) 2020: 392-409 - [c125]Yi-Hui Wu, Yi-Huan Ou-Yang, Chiung-Chu Chen, Chen-Yi Lee, Chung-Yu Wu, Ming-Dou Ker:
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals. EMBC 2020: 5188-5191 - [c124]Eugene Lee, Annie Ho, Yi-Ting Wang, Cheng-Han Huang, Chen-Yi Lee:
Cross-Domain Adaptation for Biometric Identification Using Photoplethysmogram. ICASSP 2020: 1289-1293 - [c123]Wei Chiang, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications. ISCAS 2020: 1-5 - [i2]Eugene Lee, Chen-Yi Lee:
NeuralScale: Efficient Scaling of Neurons for Resource-Constrained Deep Neural Networks. CoRR abs/2006.12813 (2020) - [i1]Eugene Lee, Evan Chen, Chen-Yi Lee:
Meta-rPPG: Remote Heart Rate Estimation Using a Transductive Meta-Learner. CoRR abs/2007.06786 (2020)
2010 – 2019
- 2019
- [j88]Zhanwei Zhong, Zipeng Li, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques. IEEE Trans. Biomed. Circuits Syst. 13(2): 292-313 (2019) - [j87]Heng-Wei Hsu, Tung-Yu Wu, Sheng Wan, Wing Hung Wong, Chen-Yi Lee:
QuatNet: Quaternion-Based Head Pose Estimation With Multiregression Loss. IEEE Trans. Multim. 21(4): 1035-1046 (2019) - [c122]Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee:
Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips. ASP-DAC 2019: 468-473 - [c121]Kit Hwa Cheah, Humaira Nisar, Vooi Voon Yap, Chen-Yi Lee:
Short-time-span EEG-based personalized emotion recognition with deep convolutional neural network. ICSIPA 2019: 78-83 - [c120]Yun-Sheng Chan, Kuan-Yu Lung, Yun-Ming Wang, Chen-Yi Lee:
Joint Capacitive Sensing and Frequency Selection for Fast Medical Tests. ISCAS 2019: 1-5 - [c119]Eugene Lee, Tsu-Jui Hsu, Chen-Yi Lee:
Centralized State Sensing using Sensor Array on Wearable Device. ISCAS 2019: 1-5 - [c118]Yun-Wen Lu, Antoon Purnal, Simon Vandenhende, Chen-Yi Lee, Ingrid Verbauwhede, Hsie-Chia Chang:
A Lightweight 1.16 pJ/bit Processor for the Authenticated Encryption Scheme KetjeSR. VLSI-DAT 2019: 1-4 - 2018
- [j86]Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu:
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control. IEEE J. Solid State Circuits 53(11): 3314-3326 (2018) - [j85]Zipeng Li, Kelvin Yi-Tse Lai, John McCrone, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee:
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 601-614 (2018) - [j84]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 968-981 (2018) - [c117]Yi-Wei Chen, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee:
Diabetic Retinopathy Detection Based on Deep Convolutional Neural Networks. ICASSP 2018: 1030-1034 - [c116]Sheng Wan, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee:
Confnet: Predict with Confidence. ICASSP 2018: 2921-2925 - [c115]Heng-Wei Hsu, Tung-Yu Wu, Wing Hung Wong, Chen-Yi Lee:
Correlation-Based Face Detection for Recognizing Faces in Videos. ICASSP 2018: 3101-3105 - [c114]Fang-Ju Ku, Tung-Yu Wu, Yen-Chin Liao, Hsie-Chia Chang, Wing Hung Wong, Chen-Yi Lee:
A 1.86mJ/Gb/query bit-plane payload machine learning processor in 90nm CMOS. VLSI-DAT 2018: 1-4 - 2017
- [j83]Chang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee:
A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications. IEEE J. Solid State Circuits 52(10): 2601-2612 (2017) - [j82]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11(3): 612-626 (2017) - [j81]Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips. IEEE Trans. Biomed. Circuits Syst. 11(6): 1380-1391 (2017) - [j80]Szu-Chi Chung, Chun-Yuan Yu, Sung-Shine Lee, Hsie-Chia Chang, Chen-Yi Lee:
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2522-2531 (2017) - [c113]Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw:
Design considerations and clinical applications of closed-loop neural disorder control SoCs. ASP-DAC 2017: 295-298 - [c112]Zipeng Li, Kelvin Yi-Tse Lai, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips. ISVLSI 2017: 146-151 - 2016
- [j79]Yingchieh Ho, Shu-Yu Hsu, Chen-Yi Lee:
A Variation-Tolerant Subthreshold to Superthreshold Level Shifter for Heterogeneous Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 161-165 (2016) - [j78]Chia-Lung Lin, Shu-Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 863-867 (2016) - [c111]Chang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee:
A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications. A-SSCC 2016: 265-268 - [c110]Chia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communications. A-SSCC 2016: 337-340 - [c109]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee:
High-level synthesis for micro-electrode-dot-array digital microfluidic biochips. DAC 2016: 146:1-146:6 - [c108]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Miroslav Pajic, Tsung-Yi Ho, Chen-Yi Lee:
Error recovery in a micro-electrode-dot-array digital microfluidic biochip? ICCAD 2016: 105 - [c107]Yingchieh Ho, Gary Wang, Kelvin Yi-Tse Lai, Yi-Wen Lu, Keng-Ming Liu, Yun-Ming Wang, Chen-Yi Lee:
Design of a micro-electrode cell for programmable lab-on-CMOS platform. ISCAS 2016: 2871-2874 - [c106]Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee:
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips. ITC 2016: 1-10 - 2015
- [j77]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 507-516 (2015) - [j76]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 301-305 (2015) - [j75]Chia-Lung Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(10): 2523-2532 (2015) - [j74]Chang-Hung Tsai, Yu-Ting Chih, Wing Hung Wong, Chen-Yi Lee:
A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1073-1077 (2015) - [j73]Szu-Chi Chung, Jing-Yu Wu, Hsing-Ping Fu, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 88-97 (2015) - [j72]Chi-Heng Yang, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1235-1244 (2015) - [j71]Kelvin Yi-Tse Lai, Yu-Tao Yang, Chen-Yi Lee:
An Intelligent Digital Microfluidic Processor for Biomedical Detection. J. Signal Process. Syst. 78(1): 85-93 (2015) - [c105]Kelvin Yi-Tse Lai, Ming-Feng Shiu, Yi-Wen Lu, Yingchieh Ho, Yu-Chi Kao, Yu-Tao Yang, Gary Wang, Keng-Ming Liu, Hsie-Chia Chang, Chen-Yi Lee:
A field-programmable lab-on-a-chip with built-in self-test circuit and low-power sensor-fusion solution in 0.35μm standard CMOS process. A-SSCC 2015: 1-4 - [c104]Xin-Ru Lee, Chih-Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications. ESSCIRC 2015: 96-99 - [c103]Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee:
A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. ISCAS 2015: 1450-1453 - [c102]Ping-Yuan Tsai, Yu-Yun Chang, Shu-Yu Hsu, Chen-Yi Lee:
An OFDM-based 29.1Mbps 0.22nJ/bit body channel communication baseband transceiver. VLSI-DAT 2015: 1-4 - 2014
- [j70]Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, Chen-Yi Lee:
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications. IEEE J. Solid State Circuits 49(4): 801-811 (2014) - [j69]Yi-Min Lin, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A 2.56 Gb/s Soft RS (255, 239) Decoder Chip for Optical Communication Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2110-2118 (2014) - [j68]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 49-61 (2014) - [c101]Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee:
A 1-100Mb/s 0.5-9.9mW LDPC convolutional code decoder for body area network. A-SSCC 2014: 229-232 - [c100]Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee:
A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring. A-SSCC 2014: 293-296 - [c99]Tzi-Dar Chiueh, Toru Shimizu, Gregory Chen, Chen-Yi Lee, Charles Hsu, Tihao Chiang, Zhihua Wang, Junghwan Choi, Jongwoo Lee, Yasumoto Tomita, Takayuki Kawahara:
What is a good way to expand a silicon value to a solution value? A-SSCC 2014: 389-394 - [c98]Chang-Hung Tsai, Hui-Hsuan Lee, Wan-Ju Yu, Chen-Yi Lee:
A 2 GOPS quad-mean shift processor with early termination for machine learning applications. ISCAS 2014: 157-160 - [c97]Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. ISCAS 2014: 409-412 - [c96]Chen-Yi Lee, Kelvin Yi-Tse Lai, Shu-Yu Hsu:
Event-driven read-out circuits for energy-efficient sensor-SoC's. VLSI-DAT 2014: 1-2 - [c95]Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee:
A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. VLSIC 2014: 1-2 - 2013
- [j67]Wen-Tsuen Chen, Youn-Long Lin, Chen-Yi Lee, Jeng-Long Chiang, Meng-Fan Chang, Shih-Chieh Chang:
Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan. IEEE Access 1: 123-130 (2013) - [j66]Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2160-2164 (2013) - [c94]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
Processor with side-channel attack resistance. ISSCC 2013: 50-51 - [c93]Kelvin Yi-Tse Lai, Yu-Tao Yang, Gary Wang, Yi-Wen Lu, Chen-Yi Lee:
A digital microfluidic processor for biomedical applications. SiPS 2013: 54-58 - 2012
- [j65]Chih-Lung Chen, Yu-Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder. IEEE J. Solid State Circuits 47(4): 817-831 (2012) - [j64]Shao-Wei Yen, Shiang-Yu Hung, Chih-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications. IEEE J. Solid State Circuits 47(9): 2246-2257 (2012) - [j63]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine. IEEE Trans. Circuits Syst. II Express Briefs 59-II(2): 103-107 (2012) - [j62]Jen-Wei Lee, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient DPA Countermeasure With Randomized Montgomery Operations for DF-ECC Processor. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 287-291 (2012) - [j61]Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, Chen-Yi Lee:
A Low-Power DCO Using Interlaced Hysteresis Delay Cells. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 673-677 (2012) - [j60]Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee:
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1615-1620 (2012) - [c92]Chia-Lin Liu, Chang-Hung Tsai, Hsiuan-Ting Wang, Yao Li, Chen-Yi Lee:
A memory-efficient architecture for intra predictor and de-blocking filter in video coding system. APCCAS 2012: 555-558 - [c91]Po-Yao Chang, Shu-Yu Hsu, Chen-Yi Lee:
A 4.88µW ECG delineator using wavelet transform for mobile healthcare application. BioCAS 2012: 376-379 - [c90]Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee:
An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. CHES 2012: 548-564 - [c89]Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee:
A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. ISCAS 2012: 1456-1459 - [c88]Yi-Huan Ou-Yang, Chien-Yu Kao, Jen-Yuan Hsu, Pangan Ting, Chen-Yi Lee:
Extrinsic data compression method for double-binary turbo codes. ISCAS 2012: 1775-1778 - [c87]Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
Stochastic decoding for LDPC convolutional codes. ISCAS 2012: 2621-2624 - [c86]Daisuke Yamaguchi, Takumi Yajima, Chen-Yi Lee, Hiromasa Shimada, Yuki Kinebuchi, Tatsuo Nakajima:
Spatial Isolation on Realtime Hypervisor using Core-local Memory. PECCS 2012: 415-421 - [c85]Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A low cost DPA-resistant 8-bit AES core based on ring oscillators. VLSI-DAT 2012: 1-4 - [c84]Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Siou-Ming Chuang, Tze-Zheng Yang, Po-Chun Liu, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee:
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications. VLSIC 2012: 156-157 - 2011
- [j59]Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee:
A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters. IEEE J. Solid State Circuits 46(11): 2514-2523 (2011) - [j58]Chien-Chen Lin, Yao Li, Chen-Yi Lee:
A Predefined Bit-Plane Comparison Coding for Mobile Video Applications. IEEE Trans. Circuits Syst. II Express Briefs 58-II(7): 437-441 (2011) - [j57]Wei-Hao Sung, Jui-Yuan Yu, Chen-Yi Lee:
A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 637-641 (2011) - [j56]Yi-Min Lin, Chi-Heng Yang, Chih-Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee:
A MPCN-Based Parallel Architecture in BCH Decoders for nand Flash Memory Devices. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 682-686 (2011) - [j55]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1113-1117 (2011) - [j54]Ching-Che Chung, Jui-Yuan Yu, Shiou-Ru Jang, Chen-Yi Lee:
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications. J. Signal Process. Syst. 64(2): 241-248 (2011) - [c83]Tsan-Wen Chen, Ping-Yuan Tsai, Jui-Yuan Yu, Chen-Yi Lee:
A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications. A-SSCC 2011: 189-192 - [c82]Shu-Yu Hsu, Yao-Lin Chen, Po-Yao Chang, Jui-Yuan Yu, Ten-Fang Yang, Ray-Jade Chen, Chen-Yi Lee:
A micropower biomedical signal processor for mobile healthcare applications. A-SSCC 2011: 301-304 - [c81]Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee:
A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence. ESSCIRC 2011: 71-74 - [c80]Chih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systems. ESSCIRC 2011: 79-82 - [c79]Tsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, Jui-Yuan Yu, Chen-Yi Lee:
A low power all-digital signal component separator for uneven multi-level LINC systems. ESSCIRC 2011: 403-406 - [c78]Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. ISCAS 2011: 713-716 - [c77]Ming-Yu Kuo, Yao Li, Chen-Yi Lee:
An area-efficient high-accuracy prediction-based CABAC decoder architecture for H.264/AVC. ISCAS 2011: 1960-1963 - [c76]Tsung-Han Lin, Yuki Kinebuchi, Alexandre Courbot, Hiromasa Shimada, Takushi Morita, Hitoshi Mitake, Chen-Yi Lee, Tatsuo Nakajima:
Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design. ISORC 2011: 241-249 - [c75]Tsung-Han Lin, Yuki Kinebuchi, Hiromasa Shimada, Hitoshi Mitake, Chen-Yi Lee, Tatsuo Nakajima:
Hardware-Assisted Reliability Enhancement for Embedded Multi-core Virtualization Design. RTCSA (2) 2011: 101-105 - [c74]Ping-Yuan Tsai, Tsan-Wen Chen, Chen-Yi Lee:
A low-power all-digital phase modulator pair for LINC transmitters. SoCC 2011: 48-51 - [c73]Tzu-Chun Shih, Tsan-Wen Chen, Wei-Hao Sung, Ping-Yuan Tsai, Chen-Yi Lee:
An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications. SoCC 2011: 371-375 - 2010
- [j53]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications. IEICE Electron. Express 7(9): 634-639 (2010) - [j52]Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang:
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. 6(4): 551-562 (2010) - [j51]Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. IEEE J. Solid State Circuits 45(2): 422-432 (2010) - [j50]Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee:
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System. IEEE J. Solid State Circuits 45(11): 2330-2340 (2010) - [j49]Chen-Fong Hsiao, Yuan Chen, Chen-Yi Lee:
A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 26-30 (2010) - [j48]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 546-550 (2010) - [j47]Shu-Yu Hsu, Jui-Yuan Yu, Chen-Yi Lee:
A Sub-10-muhboxW Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 951-955 (2010) - [c72]Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee:
A low-power radix-4 Viterbi decoder based on DCVSPG pulsed latch with sharing technique. APCCAS 2010: 1203-1206 - [c71]Jen-Wei Lee, Yao-Lin Chen, Chih-Yeh Tseng, Hsie-Chia Chang, Chen-Yi Lee:
A 521-bit dual-field elliptic curve cryptographic processor with power analysis resistance. ESSCIRC 2010: 206-209 - [c70]Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
An improved soft BCH decoder with one extra error compensation. ISCAS 2010: 3941-3944 - [c69]Chen-Yi Lee, Song-Bin Huang, Kang-Yi Lien, Ming-Yang Lin, Gwo-Bin Lee:
Tunable magnetic alginate microspheres by using a microfluidic device. NEMS 2010: 441-444
2000 – 2009
- 2009
- [j46]Tsan-Wen Chen, Jui-Yuan Yu, Chien-Ying Yu, Chen-Yi Lee:
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications. IEEE J. Solid State Circuits 44(11): 2966-2976 (2009) - [j45]Chih-Hao Liu, Chien-Ching Lin, Shao-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Trans. Circuits Syst. II Express Briefs 56-II(9): 734-738 (2009) - [j44]Hsie-Chia Chang, Chien-Ching Lin, Fu-Ke Chang, Chen-Yi Lee:
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 1960-1967 (2009) - [c68]Shao-Wei Yen, Ming-Chih Hu, Chin-Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee:
A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. CICC 2009: 191-194 - [c67]Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee:
A 1.69 Gb/s area-efficient AES crypto core with compact on-the-fly key expansion unit. ESSCIRC 2009: 404-407 - [c66]Chih-Lung Chen, Kao-Shou Lin, Hsie-Chia Chang, Wai-Chi Fang, Chen-Yi Lee:
A 11.5-Gbps LDPC decoder based on CP-PEG code construction. ESSCIRC 2009: 412-415 - [c65]Chien-Ying Yu, Jui-Yuan Yu, Chen-Yi Lee:
An eCrystal Oscillator with Self-calibration Capability. ISCAS 2009: 237-240 - [c64]Yu-Fan Lai, Tsu-Ming Liu, Yao Li, Chen-Yi Lee:
Design of an Intra Predictor with Data Reuse for High-profile H.264 Applications. ISCAS 2009: 3018-3021 - 2008
- [j43]Chih-Hao Liu, Shau-Wei Yen, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee, Yar-Sun Hsu, Shyh-Jye Jou:
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. IEEE J. Solid State Circuits 43(3): 684-694 (2008) - [j42]Yuan Chen, Yu-Wei Lin, Yu-Chi Tsao, Chen-Yi Lee:
A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems. IEEE J. Solid State Circuits 43(5): 1260-1273 (2008) - [j41]Yuan Chen, Yu-Chi Tsao, Yu-Wei Lin, Chin-Hung Lin, Chen-Yi Lee:
An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 146-150 (2008) - [j40]Jui-Yuan Yu, Ching-Che Chung, Chen-Yi Lee:
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems. IEEE Trans. Circuits Syst. II Express Briefs 55-II(9): 922-926 (2008) - [j39]Tsu-Ming Liu, Chen-Yi Lee:
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. J. Signal Process. Syst. 50(1): 69-80 (2008) - [c63]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
An all digital spread spectrum clock generator with programmable spread ratio for SoC applications. APCCAS 2008: 850-853 - [c62]Wei-Chin Lee, Yao Li, Chen-Yi Lee:
Design of a memory-based VLC decoder for portable video applications. APCCAS 2008: 1340-1343 - [c61]Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua:
Multi-mode message passing switch networks applied for QC-LDPC decoder. ISCAS 2008: 752-755 - 2007
- [j38]Lei-Fone Chen, Chen-Yi Lee:
Design of a DVB-T/H COFDM Receiver for Portable Video Applications [Topics in Circuits for Communications]. IEEE Commun. Mag. 45(8): 112-120 (2007) - [j37]Terng-Ren Hsu, Chien-Ching Lin, Terng-Yin Hsu, Chen-Yi Lee:
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 879-884 (2007) - [j36]Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Jiun-Yan Yang, Kang-Cheng Hou, Chen-Yi Lee:
A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications. IEEE J. Solid State Circuits 42(1): 161-169 (2007) - [j35]Yu-Wei Lin, Chen-Yi Lee:
Design of an FFT/IFFT Processor for MIMO OFDM Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(4): 807-815 (2007) - [j34]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications. IEEE Trans. Circuits Syst. II Express Briefs 54-II(11): 954-958 (2007) - [j33]Tsu-Ming Liu, Sheng-Zen Wang, Bai-Jue Shieh, Chen-Yi Lee:
A New Soft Variable Length Decoder for Wireless Video Transmission. IEEE Trans. Circuits Syst. Video Technol. 17(2): 224-236 (2007) - [j32]Tsu-Ming Liu, Wen-Ping Lee, Chen-Yi Lee:
An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule. IEEE Trans. Circuits Syst. Video Technol. 17(7): 937-943 (2007) - [c60]Cheng-Chi Wong, Cheng-Hao Tang, Ming-Wei Lai, Yan-Xiu Zheng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu.-T. Su:
A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. CICC 2007: 273-276 - [c59]Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee:
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. ISSCC 2007: 364-609 - [c58]Jui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, Chen-Yi Lee:
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. SoCC 2007: 305-308 - 2006
- [j31]Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Chen-Yi Lee:
A low-power dual-mode video decoder for mobile applications. IEEE Commun. Mag. 44(8): 119-126 (2006) - [j30]Pao-Lung Chen, Ching-Che Chung, Jyh-Neng Yang, Chen-Yi Lee:
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications. IEEE J. Solid State Circuits 41(6): 1275-1285 (2006) - [j29]Hsuan-Yu Liu, Chen-Yi Lee:
A Low-Complexity Synchronizer for OFDM-Based UWB System. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1269-1273 (2006) - [j28]Wen-Hsiao Peng, Tihao Chiang, Hsueh-Ming Hang, Chen-Yi Lee:
A Context Adaptive Bit-Plane Coder With Maximum-Likelihood-Based Stochastic Bit-Reshuffling Technique for Scalable Video Coding. IEEE Trans. Multim. 8(4): 654-667 (2006) - [j27]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
A low power turbo/Viterbi decoder for 3GPP2 applications. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 426-430 (2006) - [c57]Duo Sheng, Ching-Che Chung, Chen-Yi Lee:
A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications. APCCAS 2006: 105-108 - [c56]Tsu-Ming Liu, Chen-Yi Lee:
An Improved Soft-Input CAVLC Decoder for Mobile Communication Applications. APCCAS 2006: 582-585 - [c55]Shao-Ming Sun, Tsu-Ming Liu, Chen-Yi Lee:
A Self-Grouping and Table-Merging Algorithm for VLC-Based Video Decoding System. APCCAS 2006: 1567-1570 - [c54]Tsu-Ming Liu, Ching-Che Chung, Chen-Yi Lee, Ting-An Lin, Sheng-Zen Wang:
Design of a 125muW, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications. DAC 2006: 288-289 - [c53]Lei-Fone Chen, Yuan Chen, Lu-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee:
A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications. ISSCC 2006: 1002-1011 - [c52]Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang, Chen-Yi Lee:
A 125µw, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications. ISSCC 2006: 1576-1585 - 2005
- [j26]Pao-Lung Chen, Chen-Yi Lee:
A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3554-3563 (2005) - [j25]Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee:
A 1-GS/s FFT/IFFT processor for UWB applications. IEEE J. Solid State Circuits 40(8): 1726-1735 (2005) - [j24]Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee:
A portable digitally controlled oscillator using novel varactors. IEEE Trans. Circuits Syst. II Express Briefs 52-II(5): 233-237 (2005) - [j23]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
Design of a power-reduction Viterbi decoder for WLAN applications. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1148-1156 (2005) - [j22]Yen-Kuang Chen, Stella Kuei-Ann Wen, Chen-Yi Lee:
Guest Editorial: System-on-a-Chip for Multimedia Systems. J. VLSI Signal Process. 41(1): 5-7 (2005) - [c51]Chien-Ching Lin, Kai-Li Lin, Hsie-Chia Chang, Chen-Yi Lee:
A 3.33Gb/s (1200,720) low-density parity check code decoder. ESSCIRC 2005: 211-214 - [c50]Tsu-Ming Liu, Wen-Ping Lee, Chen-Yi Lee:
An area-efficient and high-throughput de-blocking filter for multi-standard video applications. ICIP (3) 2005: 1044-1049 - [c49]Ting-An Lin, Chen-Yi Lee:
Predictive equalizer design for DVB-T system. ISCAS (2) 2005: 940-943 - [c48]Ting-An Lin, Sheng-Zen Wang, Tsu-Ming Liu, Chen-Yi Lee:
An H.264/AVC decoder with 4×4-block level pipeline. ISCAS (2) 2005: 1810-1813 - [c47]Tsu-Ming Liu, Wen-Ping Lee, Ting-An Lin, Chen-Yi Lee:
A memory-efficient deblocking filter for H.264/AVC video coding. ISCAS (3) 2005: 2140-2143 - [c46]Sheng-Zen Wang, Ting-An Lin, Tsu-Ming Liu, Chen-Yi Lee:
A new motion compensation design for H.264/AVC decoder. ISCAS (5) 2005: 4558-4561 - [c45]Pao-Lung Chen, Ching-Che Chung, Chen-Yi Lee:
An all-digital PLL with cascaded dynamic phase average loop for wide multiplication range applications. ISCAS (5) 2005: 4875-4878 - [c44]Jui-Yuan Yu, Ming-Fu Sun, Terng-Yin Hsu, Chen-Yi Lee:
A novel technique for I/Q imbalance and CFO compensation in OFDM systems. ISCAS (6) 2005: 6030-6033 - 2004
- [j21]Ching-Che Chung, Chen-Yi Lee:
A new DLL-based approach for all-digital multiphase clock generation. IEEE J. Solid State Circuits 39(3): 469-475 (2004) - [j20]Yu-Wei Lin, Hsuan-Yu Liu, Chen-Yi Lee:
A dynamic scaling FFT processor for DVB-T applications. IEEE J. Solid State Circuits 39(11): 2005-2013 (2004) - [c43]Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee:
A dual mode channel decoder for 3GPP2 mobile wireless communications. ESSCIRC 2004: 483-486 - [c42]Tsu-Ming Liu, Chen-Yi Lee:
A low-complexity soft vlc decoder using performance modeling. ICIP 2004: 3233-3236 - [c41]Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
A power and area efficient multi-mode FEC processor. ISCAS (2) 2004: 253-256 - [c40]Cheng-Hung Liu, Bai-Jue Shieh, Chen-Yi Lee:
A low-power group-based VLD design. ISCAS (2) 2004: 337-340 - [c39]Wen-Hsiao Peng, Tihao Chiang, Hsueh-Ming Hang, Chen-Yi Lee:
Enhanced Stochastic Bit Reshuffling for Fine Granular Scalable Video Coding. PCM (2) 2004: 521-528 - 2003
- [j19]Hsie-Chia Chang, Chen-Yi Lee:
A Low-Power Design for Reed-Solomon Decoders. J. Circuits Syst. Comput. 12(2): 159-170 (2003) - [j18]Ching-Che Chung, Chen-Yi Lee:
An all-digital phase-locked loop for high-speed clock generation. IEEE J. Solid State Circuits 38(2): 347-351 (2003) - [j17]Yew-San Lee, Keng-Khai Ong, Chen-Yi Lee:
Error-resilient image coding (ERIC) with smart-IDCT error concealment technique for wireless multimedia transmission. IEEE Trans. Circuits Syst. Video Technol. 13(2): 176-181 (2003) - [j16]Cheng-Hsien Chen, Chen-Yi Lee:
Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware. Vis. Comput. 19(7-8): 467-479 (2003) - [c38]Chien-Ching Lin, Chia-Cho Wu, Chen-Yi Lee:
A low power and high speed Viterbi decoder chip for WLAN applications. ESSCIRC 2003: 723-726 - [c37]Hsuan-Yu Liu, Yi-Hsin Yu, Chien-Jen Hung, Temg-Yin Hsu, Chen-Yi Lee:
Combining adaptive smoothing and decision-directed channel estimation schemes for OFDM WLAN systems. ISCAS (2) 2003: 149-152 - [c36]Jhy-Neng Yang, Yi-Chang Cheng, Chen-Yi Lee:
A Design of CMOS Broadband Amplifier With High-Q Active Inductor. IWSOC 2003: 86-89 - [c35]Wei-Chang Tsai, Chun-Ming Huang, Jiann-Jenn Wang, Chen-Yi Lee:
Infrastructure for Education and Research of SOC/IP in Taiwan. MSE 2003: 150- - 2002
- [j15]Cheng-Hsien Chen, Chen-Yi Lee:
Reduce the Memory Bandwidth of 3D Graphics Hardware with a Novel Rasterizer. J. Circuits Syst. Comput. 11(4): 377-392 (2002) - [j14]Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang, Yi-Chuan Liu, Chen-Yi Lee:
Design of a wide-band frequency synthesizer based on TDC and DVC techniques. IEEE J. Solid State Circuits 37(10): 1244-1255 (2002) - [j13]Cheng-Hsien Chen, Chen-Yi Lee:
A JPEG-like texture compression with adaptive quantization for 3D graphics application. Vis. Comput. 18(1): 29-40 (2002) - [c34]Yu-Tsang Chang, Yu-Te Chou, Wei-Chang Tsai, Jiann-Jenn Wang, Chen-Yi Lee:
FPGA education and research activities in Taiwan. FPT 2002: 445-448 - [c33]Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee:
A novel DCT-based bit plane error resilient entropy coding for wireless multimedia communication. ICASSP 2002: 4182 - [c32]Keng-Khai Ong, Yew-San Lee, Chen-Yi Lee:
Error resilient image coding and smart post-processing error concealment for wireless image transmission. ICASSP 2002: 4182 - [c31]Hung-Kuo Wei, Yew-San Lee, Yen-Hsu Shih, Chen-Yi Lee:
A novel fixed bit plane error resilient image coding for wireless multimedia transmission. ICIP (3) 2002: 565-568 - [c30]Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee:
A high throughput low cost context-based adaptive arithmetic codec for multiple standards. ICIP (1) 2002: 872-875 - [c29]Yew-San Lee, Cheng-Mou Yu, Hung-Kuo Wei, Yen-Hsu Shih, Chen-Yi Lee:
A novel DCT-based bit plane error resilient entropy coding scheme and codec for wireless image communication. ISCAS (5) 2002: 121-124 - [c28]Keng-Khai Ong, Wei-Hsin Chang, Yi-Chen Tseng, Yew-San Lee, Chen-Yi Lee:
A high throughput context-based adaptive arithmetic codec for JPEG2000. ISCAS (4) 2002: 133-136 - 2001
- [j12]Hsie-Chia Chang, C. Bernard Shung, Chen-Yi Lee:
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications. IEEE J. Solid State Circuits 36(2): 229-238 (2001) - [j11]Bai-Jue Shieh, Yew-San Lee, Chen-Yi Lee:
A new approach of group-based VLC codec system with full table programmability. IEEE Trans. Circuits Syst. Video Technol. 11(2): 210-221 (2001) - [c27]Frank S. Tsai, Chen-Yi Lee:
A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system. ISCAS (4) 2001: 132-135 - [c26]Jin-Jer Jong, Chen-Yi Lee:
A novel structure for portable digitally controlled oscillator. ISCAS (1) 2001: 272-275 - [c25]Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee:
Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission. ISCAS (4) 2001: 326-329 - [c24]Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee:
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. ISCAS (4) 2001: 330-333 - [c23]Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee:
A novel subcircuit extraction algorithm by recursive identification scheme. ISCAS (5) 2001: 491-494 - [c22]Hsie-Chia Chang, Chen-Yi Lee:
An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. ISCAS (2) 2001: 649-652 - [c21]Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee:
A wideband digital frequency synthesizer. ISCAS (4) 2001: 710-713 - 2000
- [j10]Bai-Jue Shieh, Yew-San Lee, Chen-Yi Lee:
A high-throughput memory-based VLC decoder with codeword boundary prediction. IEEE Trans. Circuits Syst. Video Technol. 10(8): 1514-1521 (2000) - [c20]Yew-San Lee, Keng-Khai Ong, Wei-Shin Chang, Chen-Yi Lee:
FORTE-VLC: A forward tracing self-error correction variable length code for image coding in wireless application. EUSIPCO 2000: 1-4 - [c19]Yew-San Lee, Cheng-Mou Yu, Wei-Shin Chang, Chen-Yi Lee:
HVLC: error correctable hybrid variable length code for image coding in wireless transmission. ICASSP 2000: 2103-2106 - [c18]Yew-San Lee, Wei-Shin Chang, Hsin-Han Ho, Chen-Yi Lee:
Construction of Error Resilient Synchronization Codeword for Variable-Length Code in Image Transmission. ICIP 2000: 360-363 - [c17]Bai-Jue Shieh, Terng-Yin Hsu, Chen-Yi Lee:
A new approach of group-based VLC codec system. ISCAS 2000: 609-612
1990 – 1999
- 1999
- [j9]Terng-Yin Hsu, Bai-Jue Shieh, Chen-Yi Lee:
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit. IEEE J. Solid State Circuits 34(8): 1063-1073 (1999) - [j8]Yuan-Hau Yeh, Chen-Yi Lee:
Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 345-358 (1999) - [c16]Bai-Jue Shieh, Chen-Yi Lee:
An efficient VLC decompression scheme for user-defined coding tables. ICASSP 1999: 1961-1964 - [c15]Yuan-Hau Yeh, Chen-Yi Lee:
A New Anti-Aliasing Algorithm for Computer Graphics Images. ICIP (2) 1999: 442-446 - [c14]Wen-Shiaw Peng, Chen-Yi Lee:
An Efficient VLSI Architecture for Separable 2-D Discrete Wavelet Transform. ICIP (2) 1999: 754-758 - [c13]Cheng-Hsien Chen, Chen-Yi Lee:
A Cost-Effective Lighting Processor for 3D Graphics Application. ICIP (2) 1999: 792-796 - 1998
- [c12]Shin-Chou Juan, Chen-Yi Lee:
Entropy-constrained gradient-match vector quantization for image coding. ICASSP 1998: 2665-2668 - 1997
- [j7]Jer-Min Tsai, Hsin-Hsiung Fang, Chen-Yi Lee:
A multicasting solution for ATM video applications. IEEE Trans. Circuits Syst. Video Technol. 7(4): 675-686 (1997) - [j6]Chen-Yi Lee, Mei-Cheng Lu:
An Efficient VLSI Architecture for Full-Search Block Matching Algorithms. J. VLSI Signal Process. 15(3): 275-282 (1997) - [c11]Yuan-Hau Yeh, Chen-Yi Lee:
Buffer size optimization for full-search block matching algorithms. ASAP 1997: 76-85 - 1996
- [j5]Chen-Yi Lee, Shih-Chou Juan, Yen-Juan Chao:
Finite state vector quantization with multipath tree search strategy for image/video coding. IEEE Trans. Circuits Syst. Video Technol. 6(3): 287-294 (1996) - [c10]Yuan-Hau Yeh, Chen-Yi Lee:
Scalable VLSI architectures for full-search block matching algorithms. ICIP (2) 1996: 1035-1038 - [c9]Terng-Yin Hsu, Chen-Yi Lee:
The outage probability in DS/CDMA for cellular mobile radio with imperfect power control. PIMRC 1996: 183-187 - 1995
- [j4]Chen-Yi Lee, Jer-Min Tsai:
A shift register architecture for high-speed data sorting. J. VLSI Signal Process. 11(3): 273-280 (1995) - [c8]Mei-Cheng Lu, Chen-Yi Lee:
Semi-systolic array based motion estimation processor design. ICASSP 1995: 3299-3302 - [c7]Eddie G. Tzeng, Chen-Yi Lee:
An Efficient Memory Architecture for Motion Estimation Processor Design. ISCAS 1995: 712-715 - [c6]Yen-Juan Chao, Chen-Yi Lee:
A New Multi-Path Tree-Search FSVQ Architecture for Image/Video Sequence Coding. ISCAS 1995: 1628-1631 - 1994
- [j3]Chen-Yi Lee, Po-Wen Hsieh, Jer-Min Tsai:
High-speed median filter designs using shiftable content-addressable memory. IEEE Trans. Circuits Syst. Video Technol. 4(6): 544-549 (1994) - [c5]Ren-Yang Yang, Chen-Yi Lee:
High-Throughput Data Compressor Designs Using Content Addressable Memory. ISCAS 1994: 147-150 - [c4]Wen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee:
Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy. ISCAS 1994: 165-168 - [c3]Shih-Chou Juan, Yen-Jean Chao, Chen-Yi Lee:
Finite State Vector Quantization with Multi-Path Tree Search Strategy for Image/Video Coding. ISCAS 1994: 181-184 - 1993
- [j2]Chen-Yi Lee, Jer-Min Tsai, Shih-Chieh Hsu:
VLSI implementation of an M-array image filter based on shift register array. Integr. 16(1): 91-103 (1993) - [c2]Chen-Yi Lee, Shih-Chou Juan, Wen-Wei Yang:
An area-efficient maximum/minimum detection circuit for digital and video signal processing. ISCAS 1993: 223-226 - 1991
- [c1]Chen-Yi Lee, Francky Catthoor, Hugo De Man:
Breaking the bottleneck of sequential decoding for high-speed digital communication. ICASSP 1991: 1213-1216 - 1990
- [j1]Chen-Yi Lee, Francky Catthoor, Hugo De Man:
Efficient VLSI Architectures for a High-Performance Digital Image Communication System. IEEE J. Sel. Areas Commun. 8(8): 1481-1491 (1990)
Coauthor Index
[c123] [c118] [c114] [j80] [j78] [c110] [j77] [j76] [j75] [j73] [j72] [c105] [c104] [c103] [j69] [j68] [c101] [c100] [c97] [c95] [j66] [c94] [j65] [j64] [j63] [j62] [c90] [c89] [c87] [c85] [j56] [c81] [c80] [c78] [j52] [j51] [j50] [j48] [c72] [c71] [c70] [j45] [j44] [c68] [c67] [c66] [j43] [c61] [c60] [j27] [j23] [c51] [c43] [c41] [j19] [j12] [c22]
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