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ORCIDTakashi Nakada
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2020 – today
- 2022
[j17]Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima:
A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness. IEICE Trans. Inf. Syst. 105-D(7): 1308-1319 (2022)- 2021
- [j16]Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima:
Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks. IEICE Trans. Inf. Syst. 104-D(11): 1981-1991 (2021) - [j15]Hoang Gia Vu
, Takashi Nakada, Yasuhiko Nakashima:
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. Integr. 77: 180-192 (2021) - 2020
- [j14]Takashi Nakada, Hiroyuki Yanagihashi, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura:
An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. 103-D(2): 329-338 (2020) - [j13]Ryuta Shingai, Yuria Hiraga, Hisakazu Fukuoka, Takamasa Mitani, Takashi Nakada, Yasuhiko Nakashima:
Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing. IEICE Trans. Inf. Syst. 103-D(10): 2072-2082 (2020) - [c29]Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima:
Bayes without Bayesian Learning for Resisting Adversarial Attacks. CANDAR 2020: 221-227
2010 – 2019
- 2019
- [j12]Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima:
Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 878-885 (2019) - [c28]Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima:
GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. CANDAR 2019: 185-190 - [c27]Renyuan Zhang, Yan Chen, Takashi Nakada, Yasuhiko Nakashima:
DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon. SoCC 2019: 132-137 - 2018
- [j11]Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima:
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. IEICE Trans. Inf. Syst. 101-D(2): 288-302 (2018) - [j10]Renyuan Zhang, Noriyuki Uetake, Takashi Nakada, Yasuhiko Nakashima:
Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing. IEEE Micro 38(6): 73-82 (2018) - [c26]Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima:
Efficient Multitasking on FPGA Using HDL-Based Checkpointing. ARC 2018: 590-602 - [c25]Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima:
A programmable analog calculation unit for vector computations. COOL CHIPS 2018: 1-3 - 2017
- [j9]Takashi Nakada, Tomoki Hatanaka, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura:
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. IEICE Trans. Inf. Syst. 100-D(10): 2493-2504 (2017) - [c24]Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima:
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. FCCM 2017: 192 - [c23]Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada, Yasuhiko Nakashima:
Compression and Aggregation for Optimizing Information Transmission in Distributed CNN. CANDAR 2017: 112-118 - [c22]Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima:
A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing. CANDAR 2017: 180-186 - [c21]Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Nakamura, Kunimaro Imai, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi:
Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. VLSI-SoC 2017: 1-6 - 2016
- [j8]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. IEICE Trans. Inf. Syst. 99-D(12): 2881-2890 (2016) - [c20]Takashi Nakada, Hiroshi Nakamura, Toshifumi Nakamoto, Toru Shimizu:
Normally-off power management for sensor nodes of global navigation satellite system. ISOCC 2016: 193-194 - [c19]Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC 2016: 132-133 - [c18]Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu:
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. VLSI-SoC 2016: 1-7 - 2015
- [c17]Takashi Nakada, Hiroyuki Yanagihashi, Hiroshi Ueki, Takashi Tsuchiya, Masanori Hayashikoshi, Hiroshi Nakamura:
Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks. DSDIS 2015: 675-681 - [c16]Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura:
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD 2015: 149-156 - [c15]Yuan He, Masaaki Kondo, Takashi Nakada, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura:
Runtime multi-optimizations for energy efficient on-chip interconnections1. ICCD 2015: 455-458 - 2014
- [j7]Jun Yao, Yasuhiko Nakashima, Naveen Devisetti, Kazuhiro Yoshimura, Takashi Nakada:
A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction. IEICE Trans. Inf. Syst. 97-D(12): 3092-3100 (2014) - [j6]Takashi Nakada, Kazuya Okamoto, Toshiya Komoda, Shinobu Miwa, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu, Hiroshi Nakamura:
Design Aid of Multi-core Embedded Systems with Energy Model. Inf. Media Technol. 9(4): 419-428 (2014) - [c14]Hiroshi Nakamura, Takashi Nakada, Shinobu Miwa:
Normally-off computing project: Challenges and opportunities. ASP-DAC 2014: 1-5 - [c13]Takashi Nakada, Takuya Shigematsu, Toshiya Komoda, Shinobu Miwa, Hiroshi Nakamura, Yohei Sato, Hiroshi Ueki, Masanori Hayashikoshi, Toru Shimizu:
Data-aware power management for periodic real-time systems with non-volatile memory. NVMSA 2014: 1-6 - 2013
- [c12]Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE 2013: 1813-1818 - [c11]Toshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. ICCD 2013: 349-356 - [c10]Takashi Nakada, Shinobu Miwa, Keisuke Y. Yano, Hiroshi Nakamura:
Performance modeling for designing NoC-based multiprocessors. RSP 2013: 30-36 - 2012
- [j5]Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima:
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2319-2329 (2012) - 2011
- [j4]Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima:
An Instruction Mapping Scheme for FU Array Accelerator. IEICE Trans. Inf. Syst. 94-D(2): 286-297 (2011) - [c9]Jun Yao, Ryoji Watanabe, Kazuhiro Yoshimura, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima:
An efficient and reliable 1.5-way processor by fusion of space and time redundancies. DSN Workshops 2011: 69-74 - [c8]Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima:
LAPP: A Low Power Array Accelerator with Binary Compatibility. IPDPS Workshops 2011: 854-862 - 2010
- [c7]Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima:
An Instruction Decomposition Method for Reconfigurable Decoders. IWIA 2010: 39-47 - [c6]Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi:
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. PRDC 2010: 237-238
2000 – 2009
- 2008
- [j3]Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada:
A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions. Inf. Media Technol. 3(4): 646-660 (2008) - [j2]Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada:
A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions. IPSJ Trans. Syst. LSI Des. Methodol. 1: 33-47 (2008) - [c5]Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Functional Unit with Small Variety of Highly Reliable Cells. PRDC 2008: 353-354 - 2007
- [j1]Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima, Hiroaki Takada:
An Efficient Analysis of Worst Case Flush Timings for Branch Predictors. Inf. Media Technol. 2(3): 734-747 (2007) - [c4]Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima:
An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators. Annual Simulation Symposium 2007: 247-255 - 2006
- [c3]Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima:
Design and Implementation of aWorkload Specific Simulator. Annual Simulation Symposium 2006: 230-243 - [c2]Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada:
An accurate and efficient simulation-based analysis for worst case interruption delay. CASES 2006: 2-12 - 2004
- [c1]Takashi Nakada, Hiroshi Nakashima:
Design and Implementation of a High Speed Microprocessor Simulator BurstScalar. MASCOTS 2004: 364-372
Coauthor Index
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