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2020 – today
- 2024
[j5]Xiaoze Lin
, Liyang Lai, Huawei Li:
Parallel Static Learning Toward Heterogeneous Computing Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 983-993 (2024)- [c12]Liyang Lai, Zefan Lin, Qitao Wang:
Sideway Scan, Solving the Achilles' Heel of Scan-based Diagnosis. ITC-Asia 2024: 1-6 - 2023
- [j4]Jingbo Hu, Guohao Dai, Liuzheng Wang, Liyang Lai, Yu Huang, Huazhong Yang, Yu Wang:
Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1951-1964 (2023) - [c11]Huaxiao Liang, Xiaoze Lin, Liyang Lai, Naixing Wang, Yu Huang, Fei Yang, Yuxin Yang:
GPU-Based Concurrent Static Learning. ITC 2023: 159-165 - 2021
- [c10]Xiaoze Lin, Liyang Lai, Huawei Li:
Scalable Parallel Static Learning. ITC-Asia 2021: 1-6 - 2020
- [j3]Liyang Lai, Kun-Han Tsai, Huawei Li:
GPGPU-Based ATPG System: Myth or Reality? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 239-247 (2020) - [c9]Liyang Lai, Qiting Zhang, Kun-Han Hans Tsai, Wu-Tung Cheng:
GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. ITC-Asia 2020: 118-123
2010 – 2019
- 2015
- [j2]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) Scan Chain Stitching. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 466-479 (2015) - 2013
- [c8]Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan:
Diagnosis and Layout Aware (DLA) scan chain stitching. ITC 2013: 1-10
2000 – 2009
- 2009
- [c7]Ajay Khoche, Jay Katz, Sauro Landini, Kochen Liao, Neetu Agrawal, Glenn Plowman, Songlin Zuo, Liyang Lai, John Rowe, Thomas Zanon:
STDF Memory Fail Datalog Standard. VTS 2009: 209-214 - 2008
- [c6]Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng:
Detection and Diagnosis of Static Scan Cell Internal Defect. ITC 2008: 1-10 - 2007
- [j1]Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai:
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. 24(5): 476-485 (2007) - [c5]Liyang Lai, Wu-Tung Cheng, Thomas Rinderknecht:
Programmable Scan-Based Logic Built-In Self Test. ATS 2007: 371-377 - 2006
- [c4]Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill:
Signature Based Diagnosis for Logic BIST. ITC 2006: 1-9 - 2005
- [b1]Liyang Lai:
New Techniques for Logic Built -in Self -Test. University of Illinois Urbana-Champaign, USA, 2005 - [c3]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Hardware Ef.cient LBISTWith Complementary Weights. ICCD 2005: 479-484 - 2004
- [c2]Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Logic BIST with Scan Chain Segmentation. ITC 2004: 57-66 - [c1]Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel:
Logic BIST Using Constrained Scan Cells. VTS 2004: 199-205
Coauthor Index
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