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2010 – 2019
- 2013
[j4]Alfred L. Crouch, John C. Potter, Ajay Khoche, Jennifer Dworak:
FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System. IEEE Des. Test 30(5): 6-14 (2013)- 2010
- [c20]Jim O'Reilly, Ajay Khoche, Ernst Wahl, Bruce R. Parnas:
STIL P1450.4: A standard for test flow specification. ITC 2010: 506-515
2000 – 2009
- 2009
- [c19]Ajay Khoche, Jay Katz, Sauro Landini, Kochen Liao, Neetu Agrawal, Glenn Plowman, Songlin Zuo, Liyang Lai, John Rowe, Thomas Zanon:
STDF Memory Fail Datalog Standard. VTS 2009: 209-214 - 2008
- [c18]Ajay Khoche, Phil Burlison, John Rowe, Glenn Plowman:
A Tutorial on STDF Fail Datalog Standard. ITC 2008: 1-10 - 2006
- [j3]Ajay Khoche:
Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges. IEEE Des. Test Comput. 23(4): 315 (2006) - [c17]Andreas Leininger, Ajay Khoche, Martin Fischer, Nagesh Tamarapalli, Wu-Tung Cheng, Randy Klingenberg, Wu Yang:
The Next Step in Volume Scan Diagnosis: Standard Fail Data Format. ATS 2006: 360-368 - [c16]Ajay Khoche, Domenico Chindamo, Michael Braun, Martin Fischer:
Selective and Accurate Fail Data Capture in Compression Environment for Volume Diagnostics. ITC 2006: 1-10 - [c15]Ajay Khoche:
Session Abstract. VTS 2006: 152-153 - [c14]Ajay Khoche, Peter Muhmenthaler:
Session Abstract. VTS 2006: 288-289 - [c13]Ajay Khoche, Mike Rodgers, Pete O'Neil:
Session Abstract. VTS 2006: 426 - 2003
- [j2]Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus-Dieter Hilliges:
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits. J. Electron. Test. 19(2): 125-135 (2003) - 2002
- [c12]Erik H. Volkerink, Ajay Khoche, Subhasish Mitra:
Packet-Based Input Test Data Compression Techniques. ITC 2002: 154-163 - [c11]Ajay Khoche, Erik H. Volkerink, Jochen Rivoir, Subhasish Mitra:
Test Vector Compression Using EDA-ATE Synergies. VTS 2002: 97-102 - [c10]Erik H. Volkerink, Ajay Khoche, Jochen Rivoir, Klaus-Dieter Hilliges:
Test Economics for Multi-site Test with Modern Cost Reduction Techniques. VTS 2002: 411-416 - 2001
- [c9]Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir:
A new methodology for improved tester utilization. ITC 2001: 916-923 - [c8]Erik H. Volkerink, Ajay Khoche, Linda A. Kamas, Jochen Rivoir, Hans G. Kerkhoff:
Tackling test trade-offs from design, manufacturing to market using economic modeling. ITC 2001: 1098-1107
1990 – 1999
- 1997
- [c7]Ajay Khoche, Erik Brunvand:
ACT: A DFT Tool for Self-Timed Circuits. ITC 1997: 829-837 - [c6]Ajay Khoche, Erik Brunvand:
Critical hazard free test generation for asynchronous circuits. VTS 1997: 203-209 - 1995
- [c5]Ajay Khoche, Erik Brunvand:
Testing self-timed circuits using partial scan. ASYNC 1995: 160-169 - [c4]Sandeep Pagey, Ajay Khoche, Erik Brunvand:
DFT for fast testing of self-timed control circuits. Asian Test Symposium 1995: 382-386 - [c3]Ajay Khoche, Erik Brunvand:
A partial scan methodology for testing self-timed circuits. VTS 1995: 283-289 - 1994
- [c2]Ajay Khoche, Erik Brunvand:
Testing micropipelines. ASYNC 1994: 239-246 - 1992
- [j1]Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran:
A Behavioral Fault Simulator for Ideal. IEEE Des. Test Comput. 9(4): 14-21 (1992) - [c1]Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh:
A Behavioral Fault Simulator For Ideal. VLSI Design 1992: 137-143
Coauthor Index
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