"Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic ..."

Manish Pandey, Randal E. Bryant (1997)

> Home

Details and statistics

DOI: 10.1007/3-540-63166-6_25

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cav/PandeyB97
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cav/PandeyB97
Manish Pandey, Randal E. Bryant:
Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation. CAV 1997: 244-255

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.