"Logic circuit design with gates, LUTs and MUXs oriented to mask faults."

Anzhela Yu. Matrosova et al. (2017)

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DOI: 10.1109/EWDTS.2017.8110096

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Anzhela Yu. Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina:
Logic circuit design with gates, LUTs and MUXs oriented to mask faults. EWDTS 2017: 1-4

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