"Proposal of a timing model for CMOS logic gates driving a CRC load."

Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru (1998)

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DOI: 10.1145/288548.289083

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Akio Hirata, Hidetoshi Onodera, Keikichi Tamaru:
Proposal of a timing model for CMOS logic gates driving a CRC load. ICCAD 1998: 537-544

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