"STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies."

Rangharajan Venkatesan et al. (2014)

> Home

Details and statistics

DOI: 10.1109/ISCA.2014.6853233

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/isca/VenkatesanRVRR14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isca/VenkatesanRVRR14
Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. ISCA 2014: 253-264

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.