"Design of low-jitter 1-GHz phase-locked loops for digital clock generation."

Woogeun Rhee (1999)

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DOI: 10.1109/ISCAS.1999.780796

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Woogeun Rhee:
Design of low-jitter 1-GHz phase-locked loops for digital clock generation. ISCAS (2) 1999: 520-523

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