"A Timing Model for VLSI CMOS Circuits Verification and Optimization."

Luís Felipe Uebel, Sergio Bampi (1994)

> Home

Details and statistics

DOI: 10.1109/ISCAS.1994.408833

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/UebelB94
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/UebelB94
Luís Felipe Uebel, Sergio Bampi:
A Timing Model for VLSI CMOS Circuits Verification and Optimization. ISCAS 1994: 439-442

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.