"An adaptive write word-line pulse width and voltage modulation ..."

Daeyeon Kim et al. (2012)

> Home

Details and statistics

DOI: 10.1145/2333660.2333684

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/islped/KimCABS12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/islped/KimCABS12
Daeyeon Kim, Vikas Chandra, Robert C. Aitken, David T. Blaauw, Dennis Sylvester:
An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs. ISLPED 2012: 91-96

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.