"10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ ..."

Mark A. Ferriss et al. (2015)

> Home

Details and statistics

DOI: 10.1109/ISSCC.2015.7062991

access: closed

type: Conference or Workshop Paper

metadata version: 2019-07-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/isscc/FerrissSRAF15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isscc/FerrissSRAF15
Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. ISSCC 2015: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.