"Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) ..."

B. Chung, J. B. Kuo (2006)

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DOI: 10.1007/11847083_23

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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B. Chung, J. B. Kuo:
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique. PATMOS 2006: 237-246

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