"A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC ..."

Jai Gopal Pandey et al. (2018)

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DOI: 10.1007/978-981-13-5950-7_18

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

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Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma, Abhijit Karmakar, Raj Singh:
A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. VDAT 2018: 210-220

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