"A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 ..."

Azeez Bhavnagarwala et al. (2016)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2016.7573513

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/BhavnagarwalaIN16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/BhavnagarwalaIN16
Azeez Bhavnagarwala, Imran Iqbal, An Nguyen, David Ondricek, Vikas Chandra, Robert C. Aitken:
A 400mV active VMIN, 200mV retention VMIN, 2.8 GHz 64Kb SRAM with a 0.09 um² 6T bitcell in a 16nm FinFET CMOS process. VLSI Circuits 2016: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.