"A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and ..."

Jae-Won Nam et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573516

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen:
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. VLSI Circuits 2016: 1-2

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