"Modeling and Testing for Timing Faults in Synchronous Sequential Circuits."

Yashwant K. Malaiya, Ramesh Narayanaswamy (1984)

> Home

Details and statistics

DOI: 10.1109/MDT.1984.5005692

access: closed

type: Journal Article

metadata version: 2020-11-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/dt/MalaiyaN84
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/dt/MalaiyaN84
Yashwant K. Malaiya, Ramesh Narayanaswamy:
Modeling and Testing for Timing Faults in Synchronous Sequential Circuits. IEEE Des. Test 1(4): 62-74 (1984)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.