"Circuit design of a dual-versioning L1 data cache."

Azam Seyedi et al. (2012)

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DOI: 10.1016/J.VLSI.2011.11.015

access: closed

type: Journal Article

metadata version: 2020-02-20

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  - https://dblp.org/rec/journals/integration/SeyediACUHV12
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache. Integr. 45(3): 237-245 (2012)

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