"VLSI architecture and implementation for FS1016 CELP decoder with reduced ..."

An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin (1997)

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DOI: 10.1016/S0167-9260(97)00026-6

access: closed

type: Journal Article

metadata version: 2020-02-20

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An-Nan Suen, Jhing-Fa Wang, Jia-Lang Lin:
VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements. Integr. 24(1): 79-97 (1997)

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