"A VLSI Design Design-Synthesis Methodology at the transistor Layout Level."

Nikolaos G. Bourbakis, Mohammad Mortazavi (2005)

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type: Journal Article

metadata version: 2020-05-14

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Nikolaos G. Bourbakis, Mohammad Mortazavi:
A VLSI Design Design-Synthesis Methodology at the transistor Layout Level. Trans. SDPS 9(3): 63-85 (2005)

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