"High-Throughput Addressable Test Structure Design for Nano-Scaled CMOS ..."

Xiaolin Wang et al. (2024)

> Home

Details and statistics

DOI: 10.1109/TCSII.2024.3393475

access: closed

type: Journal Article

metadata version: 2024-10-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/WangWGRJ24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/WangWGRJ24
Xiaolin Wang, Da Wang, Lei Guo, Pengpeng Ren, Zhigang Ji:
High-Throughput Addressable Test Structure Design for Nano-Scaled CMOS Device Characterization. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4041-4045 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.