"High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue ..."

Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa (2006)

> Home

Details and statistics

DOI: 10.1007/S11227-006-6719-5

access: closed

type: Journal Article

metadata version: 2020-12-29

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tjs/AbderazekYS06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tjs/AbderazekYS06
Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa:
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. J. Supercomput. 38(1): 3-15 (2006)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.