"Variable tapered pareto buffer design and implementation allowing run-time ..."

Hua Wang et al. (2005)

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DOI: 10.1109/TVLSI.2005.859480

access: closed

type: Journal Article

metadata version: 2020-03-11

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Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene:
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 13(10): 1127-1135 (2005)

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