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2010 – 2019
- 2019
[c4]Katsuhiko Hoya, Kosuke Hatsuda, Kenji Tsuchida, Yohji Watanabe, Yusuke Shirota, Tatsunori Kanai:
A perspective on NVRAM technology for future computing system. VLSI-DAT 2019: 1-2- 2011
- [j9]Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii:
A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance. IEEE J. Solid State Circuits 46(2): 530-536 (2011) - [j8]Daisaburo Takashima, Hidehiro Shiga
, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. IEEE J. Solid State Circuits 46(9): 2171-2179 (2011) - 2010
- [j7]Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. IEEE J. Solid State Circuits 45(1): 142-152 (2010) - [c3]Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Kuniaki Sugiura, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe:
A 64Mb MRAM with clamped-reference and adequate-reference schemes. ISSCC 2010: 258-259 - [c2]Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama:
A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. ISSCC 2010: 262-263
2000 – 2009
- 2009
- [c1]Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. ISSCC 2009: 464-465
1990 – 1999
- 1997
- [j6]Toshiaki Kirihata, Hing Wong, John K. DeBrosse, Yohji Watanabe, Takahiko Hara, Munehiro Yoshida, Matthew R. Wordeman, Shuso Fujii, Yoshiaki Asao, Bo Krsnik:
Flexible test mode approach for 256-Mb DRAM. IEEE J. Solid State Circuits 32(10): 1525-1534 (1997) - 1996
- [j5]Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao:
Fault-tolerant designs for 256 Mb DRAM. IEEE J. Solid State Circuits 31(4): 558-566 (1996) - [j4]Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. IEEE J. Solid State Circuits 31(4): 567-574 (1996) - 1994
- [j3]Yohji Watanabe, Nobuo Nakamura, Shigeyoshi Watanabe:
Offset compensating bit-line sensing scheme for high density DRAM's. IEEE J. Solid State Circuits 29(1): 9-13 (1994)
1980 – 1989
- 1989
- [j2]Tohru Furuyama, Takashi Ohsawa, Yousei Nagahama, Hiroto Tanaka, Yohji Watanabe, Tohru Kimura, Kazuyoshi Muraoka, Kenji Natori:
An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application. IEEE J. Solid State Circuits 24(2): 388-393 (1989) - [j1]Yohji Watanabe, Takashi Ohsawa, Kiyofumi Sakurai, Tohru Furuyama:
A new CR-delay circuit technology for high-density and high-speed DRAMs. IEEE J. Solid State Circuits 24(4): 905-910 (1989)
Coauthor Index
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