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ORCIDIEEE Journal of Solid-State Circuits, Volume 31
Volume 31, Number 1, January 1996
- Kirk B. Ashby, Ico A. Koullias, William C. Finley, John J. Bastek, Shahriar Moinian:
High Q inductors for wireless applications in a complementary silicon bipolar process. 4-9 - Farhood Moraveji:
A wide-band, low-power, high slew rate voltage-feedback operational amplifier. 10-16 - Norihisa Yamamoto, Osamu Nakagawa, Kenji Takebuchi, Yukinori Kitamura:
An adjustment-free single-chip video signal processing LSI for VHS VCR's. 17-23 - Michael Neuhäuser, Hans-Martin Rein, Horst Wernz:
Low-noise, high-gain Si-bipolar preamplifiers for 10 Gb/s optical-fiber links-design and realization. 24-29 - Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto:
A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment. 30-37 - Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon:
A speed, power, and supply noise evaluation of ECL driver circuits. 38-45 - Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko:
A fully compensated active pull-down ECL circuit with self-adjusting driving capability. 46-53 - Zhihao Lao, Ulrich Langmann, Jens N. Albers, Erwin Schlag, Detlef Clawin:
Si bipolar 14 Gb/s 1: 4-demultiplexer IC for system applications. 54-60 - Thomas Linder, Herbert Zojer, Berthold Seger:
Fully analogue LMS adaptive notch filter in BICMOS technology. 61-69 - Douglas A. Mercer:
A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM. 70-76 - Vojin G. Oklobdzija:
An ECL gate with improved speed and low power in a BiCMOS process. 77-83 - Hitoshi Okamura, Takao Atsumo, Koichi Takeda, Masahide Takada, Kiyotaka Imai, Yasushi Kinoshita, Tom Yamazaki:
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump. 84-90 - Lawrence T. Clark, Gregory F. Taylor:
High fan-in circuit design. 91-96 - Hsin-hua Li, Nasser H. Kutkut, Deepakraj Divan, Krishna Shenai:
Design considerations of IGBT's in resonant converter applications. 97-105 - John S. Hamel:
Compact modeling of the influence of emitter stored charge on the high frequency small signal AC response of bipolar transistors using quasi-static parameters. 106-113 - Leo C. N. de Vreede, Henk C. de Graaff, Koen Mouthaan
, Marinus de Kok, Joseph L. Tauritz, Roel G. F. Baets:
Advanced modeling of distortion effects in bipolar transistors using the Mextram model. 114-121 - Eric Koenig, Jürgen Schneider, Ulrich Seiler, Uwe Erben, Hermann Schumacher:
Current-temperature feedback effects in III-V heterojunction bipolar transistors. 122-127 - Zhihao Lao, Ulrich Langmann:
Design of a low-power 10 Gb/s Si bipolar 1: 16-demultiplexer IC. 128-131 - Emmanuel Dubois, Paul-Henri Bricout, Etienne Robilliart:
Extraction method of the base series resistances in bipolar transistor in presence of current crowding. 132-135 - Colin C. McAndrew, Laurence W. Nagel:
Early effect modeling in SPICE. 136-138
Volume 31, Number 2, February 1996
- Satoshi Sakurai, Mohammed Ismail:
Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage. 146-156 - Rajesh H. Zele, David J. Allstot:
Low-power CMOS continuous-time filters. 157-168 - Michael K. Mayes, Sing W. Chin, Lee L. Stoian:
A low-power 1 MHz, 25 mW 12-bit time-interleaved analog-to-digital converter. 169-178 - Jean-Paul Eggennont, Denis De Ceuster, Denis Flandre, Bernard Gentinne, Paul G. A. Jespers, Jean-Pierre Colinge:
Design of SOI CMOS operational amplifiers for applications up to 300°C. 179-186 - David H. K. Hoe, David B. Ribner:
An auto-ranging photodiode preamplifier with 114 dB dynamic range. 187-194 - Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami:
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. 195-201 - Khaled M. Sharaf, Mohamed I. Elmasry:
Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits. 202-211 - Yasuo Arai, Masahiro Ikeno:
A time digitizer CMOS gate-array with a 250 ps time resolution. 212-220 - Richard X. Gu, Mohamed I. Elmasry:
All-N-logic high-speed true-single-phase dynamic CMOS logic. 221-229 - Per Larsson-Edefors:
A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier. 230-239 - Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikam Hida, Yasuo Ohno:
A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's. 240-246 - M. Afghahi:
A robust single phase clocking for low power, high-speed VLSI applications. 247-254 - Trond Sæther, Chung-Chih Hung, Zheng Qi, Mohammed Ismail, Oddvar Aaserud:
High speed, high linearity CMOS buffer amplifier. 255-258 - Ming-Jer Chen, Jih-Shin Ho, Tzuen-Hsi Huang:
Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling. 259-262 - Tsuneo Tsukahara, Masayuki Ishikawa, Masahiro Muraguchi:
A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator. 263-267 - Mehmet Soyuer, Keith A. Jenkins, Joachim N. Burghartz, Herschel A. Ainspan, Frank J. Canora, Slaila Ponnapalli, John F. Ewen, William E. Pence:
A 2.4-GHz silicon bipolar oscillator with integrated resonator. 268-270 - J. D. Bruce, Harry W. Li, Michael J. Dallabetta, R. Jakob Baker:
Analog layout using ALAS! 271-274 - Kjell O. Jeppson:
Comments on the metastable behavior of mismatched CMOS latches. 275-277 - Barrie Gilbert, C. Chan, H. Ling, P. Choy:
Comments on "A one volt four-quadrant analog current mode multiplier cell" [with reply]. 278
Volume 31, Number 3, March 1996
- Ted Vinko Burmas, Kenneth C. Dyer, Paul J. Hurst, Stephen H. Lewis:
A second-order double-sampled delta-sigma modulator using additive-error switching. 284-293 - David W. Cline, Paul R. Gray:
A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS. 294-303 - Tristan Reimann, François Krummenacher, Michel J. Declercq:
An 8-b, 40 msamples/s switched-current-mode track-and-hold circuit on a BiCMOS sea-of-gates array. 304-311 - Rex T. Baird, Terri S. Fiez:
A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC. 312-320 - Fuji Yang, Christian C. Enz:
A low-distortion BiCMOS seventh-order Bessel filter operating at 2.5 V supply. 321-330 - Behzad Razavi:
A study of phase noise in CMOS oscillators. 331-343 - Ranjit Gharpurey, Robert G. Meyer:
Modeling and analysis of substrate coupling in integrated circuits. 344-353 - Nishath K. Verghese, David J. Allstot, Mark A. Wolfe:
Verification techniques for substrate coupling and their application to mixed-signal IC design. 354-365 - Bernhard E. Boser, Roger T. Howe:
Surface micromachined accelerometers. 366-375 - Mehrdad Heshami, Bruce A. Wooley:
A 250-MHz skewed-clock pipelined data buffer. 376-383 - Huan-Chang Liu, Jonathan S. Min, Henry Samueli:
A low-power baseband receiver IC for frequency-hopped spread spectrum communications. 384-394 - Jeffrey T. Ludwig, S. Hamid Nawab, Anantha P. Chandrakasan:
Low-power digital filtering using approximate processing. 395-400 - Robert Rogenmoser, Qiuting Huang:
An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops. 401-409 - Jorg-Michael Green, Heinrich Klar:
A CMOS gate array architecture for digital signal processing applications. 410-418 - Chris J. Nicol, Alex G. Dickinson:
A scalable pipelined architecture for fast buffer SRAMs. 419-429 - James D. Gallia, Robert J. Landers, Ching-Hao Shaw, Terence G. W. Blake, Wally Banzha:
A flexible gate array architecture for high-speed and high-density applications. 430-436 - John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model. 437-447 - Robert R. Neff, Paul R. Gray, Alberto L. Sangiovanni-Vincentelli:
A module generator for high-speed CMOS current output digital/analog converters. 448-451 - Kumar Venkat, Liang Chen, Ichiang Lin, Piyush Mistry, Pravin Madhani:
Timing verification of dynamic circuits. 452-455 - Qiuting Huang, Robert Rogenmoser:
Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks. 456-465
Volume 31, Number 4, April 1996
- Behzad Razavi:
A 2.5-Gb/s 15-mW clock recovery circuit. 472-480 - Alfred Felder, Michael Möller, Josef Popp, Josef Böck, Hans-Martin Rein:
46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology. 481-486 - Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi:
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture. 487-493 - Hideyuki Kabuo, Minoru Okamoto, Isao Tanaka, Hiroyuki Yasoshima, Shinichi Marui, Masayuki Yamasaki, Toshio Sugimura, Katsuhiko Ueda, Toshihlro Ishikawa, Hidetoshi Suzuki, Ryuichi Asahi:
An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor. 494-503 - Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
A 286 MHz 64-b floating point multiplier with enhanced CG operation. 504-513 - Yong Moon, Deog-Kyoon Jeong:
An efficient charge recovery logic circuit. 514-522 - Tadaaki Yamauchi, Yoshikazu Morooka, Hideyuki Ozaki:
A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory. 523-530 - Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina:
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. 531-536 - Katsumi Dosaka, Akira Yamazaki, Naoya Watanabe, Hideaki Abe, Jun Ohtani, Toshiyuki Ogawa, Kazunori Ishihara, Masaki Kumanoya:
A 90-MHz 16-Mb system integrated memory with direct interface to CPU. 537-545 - Masanori Izumikawa, Masakazu Yamashina:
A current direction sense technique for multiport SRAM's. 546-551 - Hiroyuki Mizuno, Takahiro Nagano:
Driving source-line cell architecture for sub-1-V high-speed low-power applications. 552-557 - Toshiaki Kirihata, Yohji Watanabe, Hing Wong, John K. DeBrosse, Munehiro Yoshida, Daisuke Kato, Shuso Fujii, Matthew R. Wordeman, Peter Poechmueller, Stephen A. Parke, Yoshiaki Asao:
Fault-tolerant designs for 256 Mb DRAM. 558-566 - Yohji Watanabe, Ring Wong, Toshiaki Kirihata, Daisuke Kato, John K. DeBrosse, Takahiko Rara, Munehiro Yoshida, Rideo Mukai, Khandker N. Quader, Takeshi Nagai, Peter Poechmueller, Peter Pfefferl, Matthew R. Wordeman, Shuso Fujii:
A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. 567-574 - Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki:
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. 575-585 - Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto:
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. 586-591 - Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki:
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs. 592-601 - Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura:
A double-level-Vth select gate array architecture for multilevel NAND flash memories. 602-609
Volume 31, Number 5, May 1996
- Chung-Yu Wu, Heng-Shou Hsu:
The design of CMOS continuous-time VHF current and voltage-mode lowpass filters with Q-enhancement circuits. 614-624 - Eric A. M. Klumperink, Carlo T. Klein, Bas Rüggeberg, Ed J. M. van Tuijl:
AM suppression with low AM-PM conversion with the aid of a variable-gain amplifier. 625-633 - J. Francisco Duque-Carrillo, Piero Malcovati, Franco Maloberti, Raquel Pérez-Aloe, Alexander H. Reyes, Edgar Sánchez-Sinencio, Guido Torelli, José M. Valverde:
VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications. 634-645 - Vladimir Friedman, Kadaba R. Lakshmikumar, David L. Price, Tuan N. Le, Jit Kumar:
A baseband processor for IS-54 cellular telephony. 646-655 - Robert A. Hawley, Bennett C. Wong, Thu-ji Lin, Joe L. Laskowski, Henry Samueli:
Design techniques for silicon compiler implementations of high-speed FIR digital filters. 656-667 - How-Rern Lin, Yu-Chin Hsu, TingTing Hwang:
Cell height driven transistor sizing in a cell based static CMOS module design. 668-676 - Steven J. E. Wilton, Norman P. Jouppi:
CACTI: an enhanced cache access and cycle time model. 677-688 - Kenneth J. Schultz, P. Glenn Gulak:
Fully parallel integrated CAM/RAM using preclassification to enable large capacities. 689-699 - Peter Nilsson, Mats Torkelson:
A monolithic digital clock-generator for on-chip clocking of custom DSP's. 700-706 - Richard X. Gu, Mohamed I. Elmasry:
Power dissipation analysis and optimization of deep submicron CMOS digital circuits. 707-713 - Kevin W. Kobayashi, Donald K. Umemoto, Thomas R. Block, Aaron K. Oki, Dwight C. Streit:
A monolithically integrated HEMT-HBT low noise high linearity variable gain amplifier. 714-718 - Ping-Hsing Lu, Chung-Yu Wu, Ming-Kai Tsai:
Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based transresistance amplifiers. 719-725 - Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta:
Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits. 726-731 - Changku Hwang, Mohammed Ismail, Joanne DeGroat:
On-Chip IDDQ testability schemes for detecting multiple faults in CMOS ICs. 732-739 - Rajasekhar Pullela, Uddalak Bhattacharya, Scott T. Allen, Mark J. W. Rodwell:
Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optic transmission. 740-743 - Patrik Larsson:
High-speed architecture for a programmable frequency divider and a dual-modulus prescaler. 744-748 - Byungsoo Chang, Joonbae Park, Wonchan Kim:
A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops. 749-752 - Edward M. Cherry, Johan H. Huijsing, Rudi G. H. Eschauzier:
Comments on "A 100-MHz 100 dB operational amplifier with multipath nested Miller compensation structure" [and reply]. 753-754
Volume 31, Number 6, June 1996
- Chin-Chieh Chao, Bruce A. Wooley:
A 1.3-ns 32-word×32-bit three-port BiCMOS register file. 758-766 - Toshio Sunaga:
A full bit prefetch DRAM sensing circuit. 767-772 - Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko:
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. 773-783 - Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada:
A GHz MOS adaptive pipeline technique using MOS current-mode logic. 784-791 - Kazuo Yano, Yasuhiko Sasaki, Kunihito Rikino, Koichi Seki:
Top-down pass-transistor logic design. 792-803 - Akilesh Parameswar, Hiroyuki Hara, Takayasu Sakurai:
A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. 804-809 - Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko:
A 64-bit carry look ahead adder using pass transistor BiCMOS gates. 810-818 - Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray:
Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability. 819-827 - Gerhard Nebel, Ulrich Kleine, Hans-Jörg Pfleiderer:
Large bandwidth BiCMOS operational amplifiers for SC video applications. 828-834 - Haruhiko Koizumi, Atsushi Noma, Tsuyoshi Tanaka, Kunihiko Kanazawa, Daisuke Ueda:
A GaAs MMIC chip-set for mobile communications using on-chip ferroelectric capacitors. 835-840 - Pius Ng, Poras T. Balsara, Don Steiss:
Performance of CMOS differential circuits. 841-846 - Tetsuro Itakura, Tetsuya Iida:
A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier. 847-849 - Paul D. Walker, Michael M. Green:
A tunable pulse-shaping filter for use in a nuclear spectrometer system. 850-855 - Yong-Yoong Chai, Louis G. Johnson:
A 2×2 analog memory implemented with a special layout injector. 856-859 - Yoshikazu Kondo, Yuichi Koshiba, Yutaka Arima, Mitsuhiro Murasaki, Tuyoshi Yamada, Hiroyuki Amishiro, Hakuro Mori, Kazuo Kyuma:
A 1.2 GFLOPS neural network chip for high-speed neural network servers. 860-864 - David J. Comer:
A theoretical design basis for minimizing CMOS fixed taper buffer area. 865-868 - Kei-Yong Khoo, Alan Y. Kwentus, Alan N. Willson Jr.:
A programmable FIR digital filter using CSD coefficients. 869-874
Volume 31, Number 7, July 1996
- Ahmadreza Rofougaran, James Y.-C. Chang, Maryam Rofougaran, Asad A. Abidi:
A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver. 880-889 - Jan Craninckx, Michiel S. J. Steyaert:
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS. 890-897 - John B. Hughes, Kenneth W. Moulding, Judith Richardson, John Bennett, William Redman-White, Mark Bracey, Randeep Singh Soin:
Automated design of switched-current filters. 898-907 - Michael Verbeck, Christoph Zimmermann, Horst-Lothar Fiedler:
A MOS switched-capacitor ladder filter in SIMOX technology for high temperature applications up to 300°C. 908-914 - Roberto Gariboldi, Francesco Pulvirenti:
A 70 mΩ intelligent high side switch with full diagnostics. 915-923 - Christoph Kuratli, Qiuting Huang, Alice Biber:
Implementation of high peak-current IGBT gate drive circuits in VLSI compatible BiCMOS technology. 924-932 - Anton Bakker, Johan H. Huijsing:
Micropower CMOS temperature sensor with digital output. 933-937 - Raf Roovers, Michiel S. J. Steyaert:
A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter. 938-944 - Mark Bracey, William Redman-White, Judith Richardson, John B. Hughes:
A full Nyquist 15 MS/s 8-b differential switched-current A/D converter. 945-951 - Jorgen Christiansen:
An integrated high resolution CMOS timing generator based on an array of delay locked loops. 952-957 - Michel Combes, Karim Dioury, Alain Greiner:
A portable clock multiplier generator using digital CMOS standard cells. 958-965 - Gyudong Kim, Min-Kyu Kim, Byoung-Soo Chang, Wonchan Kim:
A low-voltage, low-power CMOS delay element. 966-971 - Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto:
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor. 972-980 - Dinesh Somasekhar, Kaushik Roy:
Differential current switch logic: a low power DCVS logic family. 981-991 - Riad Kanan, Bertrand Hochet, Michel J. Declercq:
Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs. 992-1000 - Marc Renaudin, Bachar El-Hassan, Alain Guyot:
A new asynchronous pipeline scheme: application to the design of a self-timed ring divider. 1001-1013 - Yusuf Leblebici:
Design considerations for CMOS digital circuits with improved hot-carrier reliability. 1014-1024 - Jung-Won Sub, Kwang-Myoung Rho, Chan-Kwang Park, Yo-Hwan Koh:
Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's. 1025-1028 - J. J. F. Rijns:
CMOS low-distortion high-frequency variable-gain amplifier. 1029-1034 - Ron Hogervorst, John P. Tero, Johan H. Hoijising:
Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode. 1035-1040 - Jürgen Oehm, M. Gräfe, T. Kettner, Klaus Schumacher:
Universal low cost controller for electric motors with programmable characteristic curves. 1041-1045 - Antoine Dupret, Eric Belhaire, Jean-Claude Rodier, Philippe Lalanne, Donald Prevost, Patrick Garda, Pierre Chavel:
An optoelectronic CMOS circuit implementing a simulated annealing algorithm. 1046-1050 - José L. Huertas, Santiago Sánchez-Solano, Iluminada Baturone, Angel Barriga:
Integrated circuit implementation of fuzzy controllers. 1051-1058 - Rafael Fried, Eyal Rosin:
A high resolution frequency multiplier for clock signal generation. 1059-1062 - Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi:
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. 1063-1066 - Hiroalti Murakami, Naoka Yano, Yukio Ootaguro, Yukio Sugeno, Maki Ueno, Yukinori Muroya, Tsuneo Aramaki:
A multiplier-accumulator macro for a 45 MIPS embedded RISC processor. 1067-1071
Volume 31, Number 8, August 1996
- Hans-Martin Rein, Michael Möller:
Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s. 1076-1090 - Makoto Nakamura, Yuhki Imai, Shoji Yamahata, Yohtaro Umeda:
Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems. 1091-1099 - Alois P. Freundorfer, Thé Linh Nguyen:
Noise in distributed MESFET preamplifiers. 1100-1111 - William B. Kuhn, F. William Stephenson, Aicha Elshabini-Riad:
A 200 MHz CMOS Q-enhanced LC bandpass filter. 1112-1122 - Hamid Reza Mehrvarz, Chee Yee Kwok:
A novel multi-input floating-gate MOS four-quadrant analog multiplier. 1123-1131 - Clemenz L. Portmann, Teresa H. Y. Meng:
Power-efficient metastability error reduction in CMOS flash A/D converters. 1132-1140 - Hakan Özdemir, Asim Kepkep, Banu Pamir, Yusuf Leblebici, Ugur Çilingiroglu:
A capacitive threshold-logic gate. 1141-1150 - H. L. Chan, Sundarar Mohan, Pinaki Mazumder, George I. Haddad:
Compact multiple-valued multiplexers using negative differential resistance devices. 1151-1156 - Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi:
Leading-zero anticipatory logic for high-speed floating point addition. 1157-1164 - Abdellatif Bellaouar, H. Touzene:
3.3-V BiCMOS current-mode logic circuits for high-speed adders. 1165-1169 - Dao-Long Chen:
A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces. 1170-1176 - Yusuf Leblebici, Hakan Özdemir, Asim Kepkep, Ugur Çilingiroglu:
A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates. 1177-1183 - Denis Deschacht, Christophe Dabrin, Daniel Auvergne:
Delay propagation effect in transistor gates. 1184-1189 - Oscar M. K. Law, C. André T. Salama:
GaAs Schmitt trigger memory cell design. 1190-1192 - Oscar M. K. Law, C. André T. Salama:
GaAs dynamic memory design. 1193-1196 - Chorng-Kuang Wang, Po-Chiun Huang, Chen-Yi Huang:
A BiCMOS limiting amplifier for SONET OC-3. 1197-1200 - Shu-Yuan Chin, Chung-Yu Wu:
A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter. 1201-1207 - A. K. Gupta, James W. Haslett, Fred N. Trofimenkoff:
A wide dynamic range continuously adjustable CMOS current mirror. 1208-1213 - Germano Nicollini, Angelo Nagari, Pierangelo Confalonieri, Carlo Crippa:
A -80 dB THD, 4 Vpp switched capacitor filter for 1.5 V battery-operated systems. 1214-1219 - Beom Kyu Ko, Kwyro Lee:
A comparative study on the various monolithic low noise amplifier circuit topologies for RF and microwave applications. 1220-1225 - Keiko Makie-Fukuda, Takanobu Anbo, Toshiro Tsukada, Tatsuji Matsuura, Masao Hotta:
Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor. 1226
Volume 31, Number 9, September 1996
- Changhyun Kim, Kensall D. Wise:
A 64-site multishank CMOS low-profile neural stimulating probe. 1230-1238 - Lisa Dron McIlrath:
A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm. 1239-1247 - Michael P. Flynn, David J. Allstot:
CMOS folding A/D converters with current-mode interpolation. 1248-1257 - James E. C. Brown, Paul J. Hurst, Lawrence Der:
A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS. 1258-1266 - Bai-Sun Kong, Joo-Sun Choi, Seog-Jun Lee, Kwyro Lee:
Charge recycling differential logic (CRDL) for low power application. 1267-1276 - Ricardo Gonzalez, Mark Horowitz:
Energy dissipation in general purpose microprocessors. 1277-1284 - Hiroyuki Yamauchi, Akira Matsuzawa:
A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme. 1285-1294 - Mel Bazes, Roni Ashuri, Ernest Knoll:
An interpolating clock synthesizer. 1295-1301 - Masayuki Nakamura, Tugio Takahashi, Takesada Akiba, Goro Kitsukawa, Makoto Morino, Toshihiro Sekiguchi, Isamu Asano, Katsuo Komatsuzaki, Yoshitaka Tadaki, Songsu Cho, Kazuhiko Kajigaya, Tadashi Tachibana, Katsuyuki Sato:
A 29-ns 64-Mb DRAM with hierarchical array architecture. 1302-1307 - Kenneth S. Szajda, Charles G. Sodini, H. Frederick Bowman:
A low noise, high resolution silicon temperature sensor. 1308-1313 - Fernando Silveira, Denis Flandre, Paul G. A. Jespers:
A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. 1314-1319 - Ion E. Opris, Gregory T. A. Kovacs:
A rail-to-rail ping-pong op-amp. 1320-1324 - Subhajit Sen, Bosco Leung:
A class-AB high-speed low-power operational amplifier in BiCMOS technology. 1325-1330 - Robert G. Meyer, William D. Mack:
Monolithic AGC loop for a 160 Mb/s transimpedance amplifier. 1331-1335 - Bernd Prégardier, Ulrich Langmann, William J. Hillery:
A 1.2-GS/s 8-b silicon bipolar track & hold IC. 1336-1339 - Domine M. W. Leenaerts, G. H. M. Joordens, Johannes A. Hegt:
A 3.3 V 625 kHz switched-current multiplier. 1340-1343 - Uwe Zillmann, Frank Herzel:
An improved SPICE model for high-frequency noise of BJTs and HBTs. 1344-1346 - Qiuting Huang:
Mixed analog/digital, FIR/IIR realization of a linear-phase lowpass filter. 1347-1350 - Andrew Marshall, Joe Devore:
Power IC with EEPROM programmable switch mode regulators. 1351-1356 - Yaochao Yang, John R. Brews:
Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations. 1357-1360 - Tadashi Maeda, Keiichi Numata, Masahiro Fujii, Masatoshi Tokushima, Shigeki Wada, Muneo Fukaishi, Masaoki Ishikawa:
An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF). 1361-1363 - Robert A. Pease, J. D. Bruce, H. W. Li, R. J. Baker:
Comments on "Analog layout using ALAS!" [and reply]. 1364-1365
Volume 31, Number 10, October 1996
- Shunji Kimura, Yuhki Imai, Yutaka Miyamoto:
Direct-coupled distributed baseband amplifier IC's for 40-Gb/s optical communication. 1374-1379 - Ruai Yu, Steve M. Beccue, P. J. Zampardi, Richard L. Pierson, Anders Petersen, Keh-Chung Wang, John E. Bowers:
A packaged broad-band monolithic variable gain amplifier implemented in AlGaAs/GaAs HBT technology. 1380-1387 - Thomas Y. K. Wong, Alois P. Freundorfer, Bruce C. Beggs, John E. Sitch:
A 10 Gb/s AlGaAs/GaAs HBT high power fully differential limiting distributed amplifier for III-V Mach-Zehnder modulator. 1388-1393 - Thomas Y. K. Wong, John E. Sitch:
A 10 Gb/s ATM data synchronizer. 1394-1399 - Jens Kargaard Madsen, Peter Stuhr Lassen:
A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI. 1400-1405 - Kazumasa Kohama, Takahiro Ohgihara, Yoshikazu Murakami:
High power DPDT antenna switch MMIC for digital cellular systems. 1406-1411 - Kevin W. Kobayashi, Robert Kasody, Aaron K. Oki, Dwight C. Streit:
A 5-10 GHz octave-band AlGaAs/GaAs HBT-Schottky diode down-converter MMIC. 1412-1418 - Huei Wang, Kwo Wei Chang, Liem T. Tran, John C. Cowles, Thomas R. Block, Eric W. Lin, G. Samuel Dow, Aaron K. Oki, Dwight C. Streit, Barry R. Allen:
Low phase noise millimeter-wave frequency sources using InP-based HBT MMIC technology. 1419-1425 - Michael Schlechtweg, William H. Haydl, Axel Bangert, Jürgen Braunstein, Paul J. Tasker, Ludger Verweyen, Hermann Massler, Wolfgang Bronner, Axel Hülsmann, Klaus Köhler:
Coplanar millimeter-wave ICs for W-band applications using 0.15 μm pseudomorphic MODFETs. 1426-1434 - Jashojiban Banik, Keng L. Wong, George L. Geannopoulos, Chung Y. Joseph Yip:
A high performance 0.35-μm 3.3-V BiCMOS technology optimized for product porting from a 0.6-μm 3.3-V BiCMOS technology. 1437-1442 - Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta:
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. 1443-1450 - Fumihiko Sato, Hiroshi Tezuka, Masaaki Soda, Takasuke Hashimoto, Tetsuyuki Suzaki, Tom Tatsumi, Takenori Morikawa, Tsutomu Tashiro:
A 2.4 Gb/s receiver and a 1: 16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor. 1451-1457 - Lakshmi S. Vempati, John D. Cressler, Jeffrey Babcock, Richard C. Jaeger, David L. Harame:
Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors. 1458-1467 - Douglas R. Frey:
Log domain filtering for RF applications. 1468-1475 - Colin C. McAndrew, Jerold A. Seitchik, Derek F. Bowers, Mark Dunn, Mark Foisy, Ian Getreu, Marc McSwain, Shahriar Moinian, James Parker, David J. Roulston, Michael Schröter, Paul van Wijnen, Lawrence F. Wagner:
VBIC95, the vertical bipolar inter-company model. 1476-1483 - Michael Schröter, David J. Walkey:
Physical modeling of lateral scaling in bipolar transistors. 1484-1492 - Martin Pfost, Hans-Martin Rein, Thomas Holzwarth:
Modeling substrate effects in the design of high-speed Si-bipolar ICs. 1493-1501 - Weinan Gao, W. Martin Snelgrove, Stephen J. Kovacic:
A 5-GHz SiGe HBT return-to-zero comparator for RF A/D conversion. 1502-1506 - Tzi-Hsiung Shu, Kantilal Bacrania, Ravindra Gokhale:
A 10-b 40-Msample/s BiCMOS A/D converter. 1507-1510 - Farhood Moraveji:
A tiny, high-speed, wide-band, voltage-feedback amplifier stable with all capacitive load. 1511-1516 - Spyros Pipilos, Yannis P. Tsividis, Josef Fenk, Yannis Papananos:
A Si 1.8 GHz RLC filter with tunable center frequency and quality factor. 1517-1525 - Nicholas J. Stessman, Bapiraju Vinnakota, Ramesh Harjani:
System-level design for test of fully differential analog circuits. 1526-1534 - Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry:
Circuit techniques for CMOS low-power high-performance multipliers. 1535-1546 - Hidetoshi Kawasaki, Stephen I. Long:
A low-power 128×1-bit GaAs FIFO for ATM packet switcher. 1547-1555 - Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter:
A parallel processing chip with embedded DRAM macros. 1556-1559 - Francesco Rezzi, Federico Montecchi, Rinaldo Castello:
A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters. 1560-1564
Volume 31, Number 11, November 1996
- Tae-Sung Jung, Young-Joon Choi, Kang-Deog Suh, Byung-Hoon Suh, Jin-Ki Kim, Young-Ho Lim, Yong-Nam Koh, Jong-Wook Park, Ki-Jong Lee, Jung-Hoon Park, Kee-Tae Park, Jhang-Rae Kim, Jeong-Hyong Yi, Hyung-Kyu Lim:
A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications. 1575-1583 - Masayoshi Ohkawa, Hiroshi Sugawara, Naoaki Sudo, Masaru Tsukiji, Ken-ichiro Nakagawa, Masato Kawata, Ken-ichi Oyama, Toshio Takeshima, Shuichi Ohya:
A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell. 1584-1589 - Takayuki Kawahara, Takashi Kobayashi, Yusuke Jyouno, Syun-ichi Saeki, Naoki Miyamoto, T. Adachi, Masataka Kato, Akihiko Sato, J. Yugami, Hitoshi Kume, Katsutaka Kimura:
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. 1590-1600 - Tohru Miwa, Hachiro Yamada, Yoshinori Hirota, Toshiya Satoh, Hideki Hara:
A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies. 1601-1609 - Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki:
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. 1610-1617 - Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure:
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. 1618-1624 - Hiraki Koike, Tetsuya Otsuki, Tohru Kimura, Masao Fukuma, Yoshihira Hayashi, Yukihiko Maejima, Kazushi Amanuma, Nobuhira Tanabe, Takeo Matsuki, Shinobu Saito, Tsuneo Takeuchi, Souta Kobayashi, Takemitsu Kunio, Takashi Hase, Yoichi Miyasaka, Nobuaki Shohata, Masahide Takada:
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme. 1625-1634 - Jei-Hwan Yoo, Chang-Hyun Kim, Kyu-Chan Lee, Kye-Hyun Kyung, Seung-Moon Yoo, Jung-Hwa Lee, Moon-Hae Son, Jin-Man Han, Bok-Moon Kang, Ejaz Haq, Sang-Bo Lee, Jai-Hoon Sim, Joung-Ho Kim, Byung-Sik Moon, Keum-Yong Kim, Jae-Gwan Park, Kyu-Phil Lee, Kang-Yoon Lee, Ki-Nam Kim, Soo-In Cho, Jong-Woo Park, Hyung-Kyu Lim:
A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. 1635-1644 - Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe:
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. 1645-1655 - Takanori Saeki, Yuji Nakaoka, Mamoru Fujita, Akihito Tanaka, Kyoichi Nagata, Kenichi Sakakibara, Tatsuya Matano, Yukio Hoshino, Kazutaka Miyano, Satoshi Isa, Shigeyuki Nakazawa, Eiichiro Kakehashi, John Mark Drynan, Masahiro Komuro, Tadashi Fukase, Haruo Iwasaki, Motohiro Takenaka, Junichi Sekine, Masahiko Igeta, Nobuko Nakanishi, Toshiro Itani, Kazuyoshi Yoshida, Hiroshi Yoshino, Syuichi Hashimoto, Tsuyoshi Yoshii, Michihiko ichinose, Tomoo imura, Masato Uziie, Shinichi Kikuchi, Kuniaki Koyama, Yukio Fukuzo, Takashi Okuda:
A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. 1656-1668 - Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama:
Design of a one-transistor-cell multiple-valued CAM. 1669-1674 - Nader Vasseghi, Kenneth Yeager, Egino Saito, Mahdi Seddighnezhad:
200-MHz superscalar RISC microprocessor. 1675-1686 - Paul E. Gronowski, William J. Bowhill, Dale R. Donchin, Randel P. Blake-Campos, David A. Carlson, Edward R. Equi, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Andy Olesin, Date J. W. Noorlag, Ronald P. Preston:
A 433-MHz 64-b quad-issue RISC microprocessor. 1687-1696 - Neela Gaddis, Jonathan Lot:
A 64-b quad-issue CMOS RISC microprocessor. 1697-1702 - James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, Gregory W. Hoeppner, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf:
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. 1703-1714 - Vincent von Kaenel, Daniel Aebischer, Christian Piguet, Evert Dijkstra:
A 320 MHz, 1.5 [email protected] V CMOS PLL for microprocessor clock generation. 1715-1722 - John G. Maneatis:
Low-jitter process-independent DLL and PLL based on self-biased techniques. 1723-1732 - Kazuhito Suguri, Toshihiro Minami, Hiroaki Matsuda, Ritsu Kusaba, Toshio Kondo, Ryota Kasai, Takumi Watanabe, Hidenuri Sato, Nobutarou Shibata, Yutaka Tashiro, Takaaki Izuoka, Atsushi Shimizu, Hiroshi Kotera:
A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding. 1733-1741 - Horng-Dar Lin, A. Anesko, B. Petryna:
A 14-Gops programmable motion estimator for H.26X video coding. 1742-1750 - Colin Chiu Wing Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods:
A 64-point Fourier transform chip for video motion compensation using phase correlation. 1751-1761 - Paul E. R. Lippens, B. De Loore, G. de Haan, P. Eeckhout, H. Huijgen, A. Loning, B. T. McSweeney, M. Verstraeien, B. Pahn, J. Kettenis:
A video signal processor for motion-compensated field-rate upconversion in consumer television. 1762-1769 - Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai:
A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. 1770-1779 - Katsuya Hasegawa, Kazutake Ohara, Akihisa Oka, Takehiro Kamada, Yasuhiro Nagaoka, Katsuhisa Yano, Eiji Yamauchi, Takao Kashiro, Tomoo Nakagawa:
Low-power video encoder/decoder chip set for digital VCRs. 1780-1788 - Ely K. Tsern, Teresa H. Meng:
A low power video-rate pyramid VQ decoder. 1789-1794 - Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada:
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application. 1795-1802 - Patrick Pai, Anthony Brewster, Asad A. Abidi:
A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels. 1803-1816 - Kavch Parsi, Robert P. Burns, Alan Chaiken, Mark Chambers, William R. Forni, David Harnishfeger, Scott Kaylor, Micheal J. Pennell, Jose O. Perez, Narendra Rao, Mark Rohrhaugh, Mike Ross, Gary L. Stuhlmiller:
A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD. 1817-1830 - Sanroku Tsukamoto, I. Dedic, Toshiaki Endo, K. y. Kikuta, K. Goto, O. Kobayashi:
A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI. 1831-1836 - Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama:
Design of a one-transistor-cell multiple-valued CAM. 1669-1674
Volume 31, Number 12, December 1996
- Ardie G. Venes, Rudy J. van de Plassche:
An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing. 1846-1853 - Paul C. Yu, Hae-Seung Lee:
A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC. 1854-1861 - Michael K. Mayes, Sing W. Chin:
A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller. 1862-1872 - Eric J. van der Zwan, Eise Carel Dijkmans:
A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range. 1873-1880 - Tom Kwan, Robert Adams, Robert Libert:
A stereo multibit ΣΔ DAC with asynchronous master-clock interface. 1881-1887 - Toshihiko Hamasaki, Yoshiaki Shinohara, Hitoshi Terasawa, Kou-Ichirou Ochiai, Masaya Hiraoka, Hideki Kanayama:
A 3-V, 2%-mW multibit current-mode ΣΔ DAC with 100 dB dynamic range. 1888-1894 - Edoardo Botti, Tiziana Mandrini, Fabrizio Stefani:
A high-efficiency 4×20 W monolithic audio amplifier for automobile radios using a complementary D-MOS BCD technology. 1895-1901 - Andreas Häberli, Michael Schneider, Piero Malcovati, Ruggero Castagnetti, Franco Maloberti, Henry Baltes:
Two-dimensional magnetic microsensor with on-chip signal processing for contactless angle measurement. 1902-1907 - A. Paul Brokaw:
A temperature sensor with single resistor set-point programming. 1908-1915 - Xavier Arreguit, André van Schaik, Franqois V. Bauduin, Marc Bidiville, Eric Raeber:
A CMOS motion detector system for pointing devices. 1916-1921 - Chye Huat Aw, Bruce A. Wooley:
A 128×128-pixel standard-CMOS image sensor with electronic shutter. 1922-1930 - Susanne A. Paul, Hae-Seung Lee:
A 9-b charge-to-digital converter for integrated image sensors. 1931-1938 - Andrew N. Karanicolas:
A 2.7-V 900-MHz CMOS LNA and mixer. 1939-1944 - David H. Shen, Chien-Meen Hwang, Bruce B. Lusignan, Bruce A. Wooley:
A 900-MHz RF front-end with integrated discrete-time filtering. 1945-1954 - Christopher Dennis Hull, Joo Leong Tham, Robert Ray Chu:
A direct-conversion receiver for 900 MHz (ISM band) spread-spectrum digital cordless telephone. 1955-1963 - Kazuya Yamamoto, Kosei Maemura, Nobuyuki Kasai, Yutaka Yoshii, Yukio Miyazaki, Masatoshi Nakayama, Noriko Ogata, Tadashi Takagi, Mutsuyuki Otsubo:
A single-chip GaAs RF transceiver for 1.9-GHz digital mobile communication systems. 1964-1973 - Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi:
A 1.9-GHz single chip IF transceiver for digital cordless phones. 1974-1980 - Armond Hairapetian:
An 81-MHz IF receiver in CMOS. 1981-1986 - Jan-Erik Eklund, Ragnar Arvidsson:
A multiple sampling, single A/D conversion technique for I/Q demodulation in CMOS. 1987-1994 - Kevin S. Donnelly, Yiu-Fai Chan, John T. C. Ho, Chanh Tran, Samir Patel, Benedict Lau, Jun Kim, Pak Shing Chau, Charlie Huang, Jason Wei, Leung Yu, Richard Tarver, Rakhee Kulkarni, Donald Stark, Mark Johnson:
A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC. 1995-2003 - Albert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin:
Single-chip 4×500-MBd CMOS transceiver. 2004-2014 - Chih-Kong Ken Yang, Mark A. Horowitz:
A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links. 2015-2023 - Masakazu Kurisu, Makoto Kaneko, Tetsuyuki Suzaki, Akira Tanabe, Mitsuhiro Togo, Akio Furukawa, Takao Tamura, Ken Nakajima, Kazuyoshi Yoshida:
2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology. 2024-2029 - Gil-Cho Ahn, Hee-Cheol Choi, Shin-Il Lim, Seung-Hoon Lee, Chul-Dong Lee:
A 12-b, 10-MHz, 250-mW CMOS A/D converter. 2030-2035 - Orhan Norman:
A band-pass delta-sigma modulator for ultrasound imaging at 160 MHz clock rate. 2036-2041 - Mehmet Soyuer, Keith A. Jenkins, Joachim N. Burghartz, Michael D. Hulvey:
A 3-V 4-GHz nMOS voltage-controlled oscillator with integrated resonator. 2042-2045 - R. H. Nixon, Sabrina E. Kemeny, Bedabrata Pain, Craig O. Staller, Eric R. Fossum:
256×256 CMOS active pixel sensor camera-on-a-chip. 2046-2050 - Hiroshi Tanimoto, Tetsuro Itakura, Takashi Ueno, Akira Yasuda, Kazuhiro Oda:
An offset-free LPF for π/4-shift QPSK signal generator. 2051-2055 - Jürgen Hauenschild, Claus Dorschky, Timo Winkler von Mohrenfels, Roland Seitz:
A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1: 4-demultiplexer with external VCO. 2056-2059 - Gerard M. Blair:
Comments on "A robust single phase clocking for low power, high-speed VLSI applications" [and reply]. 2060-2061 - M. Afghahi:
Author's Reply to Comments on "A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applica. 2061
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