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2010 – 2019
- 2014
[c14]Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A 360-degree panoramic video system design. VLSI-DAT 2014: 1-4- 2013
- [j4]Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo:
Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization. J. Signal Process. Syst. 72(1): 17-33 (2013) - [c13]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu
, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c12]Jui-Sheng Lee, Yuan-Hsiang Miao, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A view scalable multi-view video decoder system. VLSI-DAT 2013: 1-4 - 2012
- [j3]Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo:
A Verification-Aware Design Methodology for Thread Pipelining Parallelization. IEICE Trans. Inf. Syst. 95-D(10): 2505-2513 (2012) - [j2]Cheng-An Chien, Guo-An Jian, Hsiu-Cheng Chang, Kuan-Hung Chen, Jiun-In Guo:
High efficiency data access system architecture for deblocking filter supporting multiple video coding standards. IEEE Trans. Consumer Electron. 58(2): 670-678 (2012) - [c11]Jui-Sheng Lee, Sheng-Han Wang, Chih-Tai Chou, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
An inter-frame/inter-view cache architecture design for multi-view video decoders. APSIPA 2012: 1-4 - [c10]Cheng-Yen Chang, Cheng-An Chien, Hsiu-Cheng Chang, Jia-Wei Chen, Jiun-In Guo:
A two level mode decision algorithm for H.264 high profile intra encoding. ISCAS 2012: 508-511 - [c9]Jui-Sheng Lee, Guo-An Jian, Cheng-An Chien, Peng-Sheng Chen, Jiun-In Guo:
3D depth map generation for embedded stereo applications. VCIP 2012: 1-6 - 2011
- [c8]Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jia-Wei Chen, Cheng-Yen Chang, Jiun-In Guo, Jinn-Shyan Wang, Ching-Hwa Cheng:
A H.264/MPEG-2 dual mode video decoder chip supporting temporal/spatial scalable video. ASP-DAC 2011: 73-74 - [c7]Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism. ASP-DAC 2011: 85-86 - [c6]Yu-Tzu Tsai, Cheng-Chih Tsai, Cheng-An Chien, Ching-Hwa Cheng, Jiun-In Guo:
A low-power management technique for high-performance domino circuits. ASP-DAC 2011: 93-94
2000 – 2009
- 2009
- [j1]Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications. ACM Trans. Design Autom. Electr. Syst. 14(1): 17:1-17:17 (2009) - [c5]Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip. ASP-DAC 2009: 125-126 - [c4]Hsiu-Cheng Chang, Jia-Wei Chen, Yao-Chang Yang, Cheng-An Chien, Tzu-Chun Chang, Jinn-Shyan Wang, Jiun-In Guo:
A Dynamic Quality-scalable H.264 Video Encoder. ISCAS 2009: 1932 - [c3]Cheng-An Chien, Chih-Da Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng:
A Multi-standard Video Decoder for High Definition Video Applications. ISCAS 2009: 1933 - [c2]Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A High Throughput Deblocking Filter Design Supporting Multiple Video Coding Standards. ISCAS 2009: 2377-2380 - 2008
- [c1]Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo:
A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding. APCCAS 2008: 312-315
Coauthor Index
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