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ORCIDElizabeth M. Rudnick
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2000 – 2009
- 2004
[j17]Dirk Niggemeyer, Elizabeth M. Rudnick:
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing. IEEE Trans. Computers 53(9): 1134-1146 (2004)- 2003
- [j16]Dirk Niggemeyer, Elizabeth M. Rudnick:
A data acquisition methodology for on-chip repair of embedded memories. ACM Trans. Design Autom. Electr. Syst. 8(4): 560-576 (2003) - 2002
- [c46]Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick:
Low-cost sequential ATPG with clock-control DFT. DAC 2002: 243-248 - [c45]Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick:
Functional Test Generation For Digital Integrated Circuits Using A Genetic Algorithm. GECCO 2002: 1275 - [c44]Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabeth M. Rudnick:
A Genetic Testing Framework for Digital Integrated Circuits. ICTAI 2002: 521-526 - 2001
- [j15]Franco Fummi, Marco Boschini, Xiaoming Yu, Elizabeth M. Rudnick:
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach. J. Electron. Test. 17(3-4): 321-330 (2001) - [j14]Dirk Niggemeyer, Kevin J. Stephano, Elizabeth M. Rudnick:
Use of a field programmable gate array for education in manufacturing test and automatic test equipment. IEEE Trans. Educ. 44(3): 239-245 (2001) - [j13]Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty:
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. ACM Trans. Design Autom. Electr. Syst. 6(4): 471-489 (2001) - [c43]Mrinal Bose, Jongshin Shin, Elizabeth M. Rudnick, Todd Dukes, Magdy Abadir:
A genetic approach to automatic bias generation for biased random instruction generation. CEC 2001: 442-448 - [c42]Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir:
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. IOLTW 2001: 65- - [c41]Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici:
At-speed logic BIST using a frozen clock testing strategy. ITC 2001: 64-71 - [c40]Miron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick:
Sequential ATPG Using Combinational Algorithms. LATW 2001: 100-106 - [c39]Dirk Niggemeyer, Elizabeth M. Rudnick:
Automatic Generation of Diagnostic March Tests. VTS 2001: 299-305 - 2000
- [j12]Ta-Chung Chang, Vikram Iyengar, Elizabeth M. Rudnick:
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors. J. Electron. Test. 16(1-2): 13-27 (2000) - [j11]Elizabeth M. Rudnick, Miron Abramovici:
Compact Test Generation Using a Frozen Clock Testing Strategy. J. Inf. Sci. Eng. 16(5): 703-717 (2000) - [j10]Jue Wu, Elizabeth M. Rudnick:
Bridge fault diagnosis using stuck-at fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(4): 489-495 (2000) - [j9]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Dynamic state traversal for sequential circuit test generation. ACM Trans. Design Autom. Electr. Syst. 5(3): 548-565 (2000) - [j8]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Peak power estimation of VLSI circuits: new peak power measures. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 435-439 (2000) - [c38]Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick:
Diagnostic Testing of Embedded Memories Using BIST. DATE 2000: 305-309 - [c37]Marco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick:
Combining symbolic and genetic techniques for efficient sequential circuit test generation. ETW 2000: 105-110 - [c36]Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick:
Diagnostic test generation for sequential circuits. ITC 2000: 225-234 - [c35]Dirk Niggemeyer, Elizabeth M. Rudnick, Michael Redeker:
Diagnostic Testing of Embedded Memories Based on Output Tracing. MTDT 2000: 113-118
1990 – 1999
- 1999
- [j7]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. IEEE Trans. Computers 48(3): 311-322 (1999) - [j6]Elizabeth M. Rudnick, Janak H. Patel:
Efficient Techniques for Dynamic Test Sequence Compaction. IEEE Trans. Computers 48(3): 323-330 (1999) - [c34]Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici:
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. DATE 1999: 747- - [c33]Jue Wu, Gary S. Greenstein, Elizabeth M. Rudnick:
A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis. DATE 1999: 780-781 - [c32]Jue Wu, Elizabeth M. Rudnick:
A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults. VLSI Design 1999: 498-505 - [r1]Vikram Iyengar, Elizabeth M. Rudnick:
Microprocessor Design Verification. The VLSI Handbook 1999 - 1998
- [j5]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 239-254 (1998) - [c31]Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno
, Paolo Prinetto, Matteo Sonza Reorda:
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. DATE 1998: 570-576 - [c30]Fulvio Corno, Janak H. Patel, Elizabeth M. Rudnick, Matteo Sonza Reorda, Roberto Vietti:
Enhancing topological ATPG with high-level information and symbolic techniques. ICCD 1998: 504-509 - [c29]Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel:
Partial Scan Selection Based on Dynamic Reachability and Observability Information. VLSI Design 1998: 174-180 - 1997
- [j4]Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann:
A genetic algorithm framework for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1034-1044 (1997) - [c28]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Sequential circuit test generation using dynamic state traversal. ED&TC 1997: 22-28 - [c27]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Effects of delay models on peak power estimation of VLSI sequential circuits. ICCAD 1997: 45-51 - [c26]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
K2: an estimator for peak sustainable power of VLSI circuits. ISLPED 1997: 178-183 - [c25]Elizabeth M. Rudnick, Janak H. Patel:
Putting the Squeeze on Test Sequences. ITC 1997: 723-732 - [c24]Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel:
Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. Workshop on Parallel and Distributed Simulation 1997: 30-37 - [c23]Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design 1997: 475-481 - [c22]Elizabeth M. Rudnick, Janak H. Patel:
Overcoming the Serial Logic Simulation Bottleneck in Parallel Fault Simulation. VLSI Design 1997: 495-503 - [c21]Charles R. Graham, Elizabeth M. Rudnick, Janak H. Patel:
Dynamic Fault Grouping for PROOFS: A Win for Large Sequential Circuits. VLSI Design 1997: 542-544 - [c20]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. VTS 1997: 188-195 - [c19]Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. VTS 1997: 274-281 - [c18]Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel:
Static logic implication with application to redundancy identification. VTS 1997: 288-295 - 1996
- [j3]Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi:
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. IEEE Trans. Computers 45(11): 1248-1256 (1996) - [c17]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Alternating Strategies for Sequential Circuit ATPG. ED&TC 1996: 368-374 - [c16]Elizabeth M. Rudnick, Janak H. Patel:
Simulation-based techniques for dynamic test sequence compaction. ICCAD 1996: 67-73 - [c15]Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel:
Enhancing high-level control-flow for improved testability. ICCAD 1996: 322-328 - [c14]Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel:
Testability Insertion in Behavioral Descriptions. ISSS 1996: 139-144 - [c13]Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz:
On Potential Fault Detection in Sequential Circuits. ITC 1996: 142-149 - [c12]Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
Automatic test generation using genetically-engineered distinguishing sequences. VTS 1996: 216-223 - [c11]Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel:
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. VTS 1996: 456-462 - 1995
- [j2]Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel:
Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 333-338 (1995) - [c10]Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel:
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. DAC 1995: 133-138 - [c9]Elizabeth M. Rudnick, Janak H. Patel:
Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation. DAC 1995: 183-188 - [c8]Elizabeth M. Rudnick, Janak H. Patel:
A genetic approach to test application time reduction for full scan and partial scan circuits. VLSI Design 1995: 288-293 - 1994
- [j1]Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel:
An observability enhancement approach for improved testability and at-speed test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 1051-1056 (1994) - [c7]Elizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann:
Sequential Circuit Test Generation in a Genetic Algorithm Framework. DAC 1994: 698-704 - [c6]Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel:
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC 1994: 40-45 - 1993
- [c5]Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel:
Non-Scan Design-for-Testability Techniques for Sequential Circuits. DAC 1993: 236-241 - [c4]Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer:
A Fast and Accurate Gate-Level Transient Fault Simulation Environment. FTCS 1993: 310-319 - 1992
- [c3]Elizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel:
Diagnostic Fault Simulation of Sequential Circuits. ITC 1992: 178-186 - [c2]Elizabeth M. Rudnick, Vivek Chickermane, Janak H. Patel:
Probe point insertion for at-speed test. VTS 1992: 223-228 - 1991
- [c1]Elizabeth M. Rudnick, Thomas M. Niermann, Janak H. Patel:
Methods for Reducing Events in Sequential Circuit Fault Simulation. ICCAD 1991: 546-549
Coauthor Index
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