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ORCIDTatiana Gadelha Serra dos Santos
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2000 – 2009
- 2009
[j2]Cristiano Bonato Both
, Cristiano Battisti, Felipe A. Kuentzer, Tatiana Gadelha Serra dos Santos, Rafael R. dos Santos:
FPGA implementation and performance evaluation of an RFC 2544 compliant Ethernet test set. Int. J. High Perform. Syst. Archit. 2(2): 107-115 (2009)- 2008
- [c7]Henrique C. Freitas, Philippe Olivier Alexandre Navaux, Tatiana Gadelha Serra dos Santos:
NOC architecture design for multi-cluster chips. FPL 2008: 53-58 - 2007
- [c6]Fabiano Hessel, César A. M. Marcon, Tatiana Gadelha Serra dos Santos:
High Level RTOS Scheduler Modeling for a Fast Design Validation. ISVLSI 2007: 461-466 - 2006
- [j1]Fabiano Hessel, Vitor M. da Rosa, Carlos Eduardo Reif, César A. M. Marcon, Tatiana Gadelha Serra dos Santos:
Scheduling refinement in abstract RTOS models. ACM Trans. Embed. Comput. Syst. 5(2): 342-354 (2006) - [c5]Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana Gadelha Serra dos Santos, Sergio Bampi, Altamiro Amadeu Susin:
FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. FPL 2006: 1-6 - 2005
- [c4]Tatiana Gadelha Serra dos Santos, Sergio Bampi, Philippe Olivier Alexandre Navaux:
Reusing Traces in a Dynamic Conditional Execution Architecture. SBAC-PAD 2005: 126-133 - 2004
- [b1]Tatiana Gadelha Serra dos Santos:
Reusing values in a dynamic conditional execution architecture. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil, 2004 - 2003
- [c3]Rafael R. dos Santos, Tatiana Gadelha Serra dos Santos, Maurício L. Pilla, Philippe Olivier Alexandre Navaux, Sergio Bampi, Mario Nemirovsky:
Complex Branch Profiling for Dynamic Conditional Execution. SBAC-PAD 2003: 28-35 - 2001
- [c2]Ronaldo Gonçalves, Maurício L. Pilla, Guilherme Dal Pizzol, Tatiana Gadelha Serra dos Santos, Philippe Olivier Alexandre Navaux, Rafael Santos:
Evaluating the Effects of Branch Prediction Accuracy on the Performance of SMT Architectures. PDP 2001: 355-362 - 2000
- [c1]Tatiana Gadelha Serra dos Santos, Sergio Bampi:
Analyzing Instruction Prefetch Schemes in Superscalar Architectures. PDPTA 2000
Coauthor Index
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