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ORCIDGabriel L. Nazar
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- affiliation (PhD 2013): Federal University of Rio Grande do Sul (UFRGS), Institute of Informatics, Porto Alegre, Brazil
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2020 – today
- 2024
[c43]Victor Sberse Guerra, Gabriel Luca Nazar:
FPGAs for Network Function Virtualization: Challenges in Placement and Partitioning. SBCCI 2024: 1-5- 2023
- [j14]Filipe Bachini Lopes
, Alberto E. Schaeffer-Filho, Gabriel Luca Nazar:
Modular VNF Components Acceleration With FPGA Overlays. IEEE Trans. Netw. Serv. Manag. 20(1): 846-857 (2023) - [j13]Marcos T. Leipnitz, Gabriel L. Nazar:
Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 16(4): 61:1-61:28 (2023) - [c42]Níkolas P. Schuster, Gabriel L. Nazar:
GRASP-based High-Level Synthesis Design Space Exploration for FPGAs. SBESC 2023: 1-6 - [p1]Luigi Carro, Gabriel Luca Nazar:
Desafios para a Computação Energeticamente Eficiente. Escola de Computação PPGC/UFRGS 50 Anos 2023: 79-96 - 2022
- [c41]Rafael Billig Tonetto, Antonio Carlos Schneider Beck, Gabriel L. Nazar:
SNAP: Selective NTV Heterogeneous Architectures for Power-Efficient Edge Computing. DSD 2022: 357-364 - 2021
- [c40]Filipe Bachini Lopes, Gabriel Luca Nazar, Alberto E. Schaeffer-Filho:
VNFAccel: An FPGA-based Platform for Modular VNF Components Acceleration. IM 2021: 250-258 - [c39]Gabriel L. Nazar, Pedro H. Kopper, Marcos T. Leipnitz, Ben H. H. Juurlink:
Lightweight Dual Modular Redundancy through Approximate Computing. SBESC 2021: 1-8 - 2020
- [j12]Gabriel S. Niemiec, Luis M. S. Batista, Alberto E. Schaeffer-Filho, Gabriel L. Nazar:
A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions. IEEE Commun. Surv. Tutorials 22(1): 504-525 (2020) - [j11]Tiago Trevisan Jost, Gabriel Luca Nazar, Luigi Carro:
SoMMA: A software-managed memory architecture for multi-issue processors. Microprocess. Microsystems 77: 103139 (2020) - [c38]Marcos T. Leipnitz, Gabriel L. Nazar:
High-level synthesis of throughput-optimized and energy-efficient approximate designs. CF 2020: 221-224 - [c37]Rafael Billig Tonetto, Hiago Mayk G. de A. Rocha, Gabriel L. Nazar, Antonio Carlos Schneider Beck:
A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores. DAC 2020: 1-6 - [c36]Marcos T. Leipnitz, Gabriel L. Nazar:
Throughput-Oriented Spatio-Temporal Optimization in Approximate High-Level Synthesis. ICCD 2020: 316-323 - [c35]Wagner Penny, Guilherme Corrêa, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Gabriel L. Nazar, Bruno Zatt:
Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC. ISCAS 2020: 1-5 - [c34]Rafael Billig Tonetto, Hiago Mayk G. de A. Rocha, Bruno Zatt, Antonio Carlos Schneider Beck, Gabriel L. Nazar:
A Reliability-Oriented Machine Learning Strategy for Heterogeneous Multicore Application Mapping. ISCAS 2020: 1-5 - [c33]Marcos T. Leipnitz, Murilo R. Perleberg, Marcelo Schiavon Porto, Gabriel L. Nazar:
Enhancing Real-Time Motion Estimation through Approximate High-Level Synthesis. ISVLSI 2020: 30-35 - [c32]Ricardo Coelho, Felipe Tanus, Álvaro F. Moreira, Gabriel L. Nazar:
ACQuA: A Parallel Accelerator Architecture for Pure Functional Programs. ISVLSI 2020: 346-351 - [c31]Hiago Rocha, Guilherme Korol, Michael Guilherme Jordan, Arthur M. Krause, Ronaldo Silveira, Caio Vieira, Philippe O. A. Navaux, Gabriel L. Nazar, Luigi Carro, Antonio Carlos Schneider Beck:
Firefly: An Open-source Rocket-based Intermittent Framework. SBCCI 2020: 1-6
2010 – 2019
- 2019
- [j10]Marcos T. Leipnitz, Gabriel L. Nazar:
High-Level Synthesis of Approximate Designs under Real-Time Constraints. ACM Trans. Embed. Comput. Syst. 18(5s): 59:1-59:21 (2019) - [c30]Marcos T. Leipnitz, Gabriel L. Nazar:
High-Level Synthesis of Resource-oriented Approximate Designs for FPGAs. DAC 2019: 126 - [c29]Wagner Penny, Jones Goebel, Douglas Corrêa, Anderson Martins, Gabriel L. Nazar, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt:
Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation. ICECS 2019: 162-165 - [c28]Douglas Maciel Cardoso, Rafael Billig Tonetto, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck:
Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors. ICECS 2019: 201-204 - [c27]Eduardo Nunes de Souza, Gabriel L. Nazar:
Cost-effective Resilient FPGA-based LDPC Decoder Architecture. IOLTS 2019: 84-89 - [c26]Rafael Billig Tonetto, Douglas Maciel Cardoso, Marcelo Brandalero, Luciano Agostini, Gabriel L. Nazar, José Rodrigo Azambuja, Antonio Carlos Schneider Beck:
A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors. VLSI-SoC 2019: 287-292 - 2018
- [j9]Marcos T. Leipnitz, Gabriel L. Nazar:
Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching. J. Electron. Test. 34(4): 487-506 (2018) - [j8]Leonardo Pereira Santos, Gabriel Luca Nazar, Luigi Carro:
Repair of FPGA-Based Real-Time Systems With Variable Slacks. ACM Trans. Design Autom. Electr. Syst. 23(2): 19:1-19:20 (2018) - [c25]Rafael Billig Tonetto, Gabriel L. Nazar, Antonio Carlos Schneider Beck:
Precise evaluation of the fault sensitivity of OoO superscalar processors. DATE 2018: 613-616 - 2017
- [j7]Leonardo Pereira Santos, Gabriel L. Nazar, Luigi Carro:
Exploring redundancy granularities to repair real-time FPGA-based systems. Microprocess. Microsystems 51: 264-274 (2017) - [c24]Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
An energy-efficient memory hierarchy for multi-issue processors. DATE 2017: 368-373 - 2016
- [j6]Gabriel L. Nazar:
SBESC 2015 guest editors' introduction. Des. Autom. Embed. Syst. 20(4): 267 (2016) - [j5]Thiago Santini, Paolo Rech, Gabriel Luca Nazar, Flávio Rech Wagner:
Beyond Cross-Section: Spatio-Temporal Reliability Analysis. ACM Trans. Embed. Comput. Syst. 15(1): 3:1-3:16 (2016) - [j4]Ronaldo Rodrigues Ferreira, Gabriel L. Nazar, Jean da Rolt, Álvaro F. Moreira, Luigi Carro:
Live-Out Register Fencing: Interrupt-Triggered Soft Error Correction Based on the Elimination of Register-to-Register Communication. ACM Trans. Embed. Comput. Syst. 15(3): 60:1-60:25 (2016) - [c23]Leonardo P. Santos, Gabriel L. Nazar, Luigi Carro:
Low Cost Dynamic Scrubbing for Real-Time Systems. ARC 2016: 144-156 - [c22]Marcos T. Leipnitz, Eduardo Nunes de Souza, Gabriel L. Nazar:
Low cost resilient regular expression matching on FPGAs. DFT 2016: 75-80 - [c21]Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
Scalable memory architecture for soft-core processors. ICCD 2016: 396-399 - [c20]Marcos T. Leipnitz, L. H. Geferson, Gabriel L. Nazar:
A fault injection platform for FPGA-based communication systems. LASCAS 2016: 59-62 - [c19]Tiago T. Jost, Gabriel L. Nazar, Luigi Carro:
Improving performance in VLIW soft-core processors through software-controlled scratchpads. SAMOS 2016: 172-179 - [c18]Levi H. S. Lelis, Richard Anthony Valenzano, Gabriel L. Nazar, Roni Stern:
Searching with a Corrupted Heuristic. SOCS 2016: 63-71 - 2015
- [j3]Gabriel L. Nazar:
Improving FPGA repair under real-time constraints. Microelectron. Reliab. 55(7): 1109-1119 (2015) - [j2]Gabriel Luca Nazar, Leonardo Pereira Santos, Luigi Carro:
Fine-Grained Fast Field-Programmable Gate Array Scrubbing. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 893-904 (2015) - [c17]Ronaldo Rodrigues Ferreira, Ernesto Sánchez, Jean da Rolt, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro, Matteo Sonza Reorda:
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture. LATS 2015: 1-6 - 2014
- [j1]Fábio P. Itturriet, Gabriel L. Nazar, Ronaldo Rodrigues Ferreira, Álvaro Freitas Moreira, Luigi Carro:
Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems. ACM Trans. Reconfigurable Technol. Syst. 7(3): 25:1-25:17 (2014) - [c16]Ronaldo Rodrigues Ferreira, Thomas Klotz, Thilo Vörtler, Jean da Rolt, Gabriel L. Nazar, Álvaro Freitas Moreira, Luigi Carro, Karsten Einwich:
Reliable execution of statechart-generated correct embedded software under soft errors. DDECS 2014: 147-152 - [c15]Ronaldo Rodrigues Ferreira, Jean da Rolt, Gabriel L. Nazar, Álvaro Freitas Moreira, Luigi Carro:
Adaptive Low-Power Architecture for High-Performance and Reliable Embedded Computing. DSN 2014: 538-549 - [c14]Thiago Santini, Paolo Rech, Gabriel L. Nazar, Luigi Carro, Flávio Rech Wagner:
Reducing embedded software radiation-induced failures through cache memories. ETS 2014: 1-6 - [c13]Giovanni Bruni, Paolo Rech, Lucas A. Tambara, Gabriel L. Nazar, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, Alessandro Paccagnella:
Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivity. VLSI-SoC 2014: 1-6 - 2013
- [c12]Gabriel L. Nazar, Leonardo P. Santos, Luigi Carro:
Scrubbing unit repositioning for fast error repair in FPGAs. CASES 2013: 2:1-2:10 - [c11]Gabriel L. Nazar, Leonardo P. Santos, Luigi Carro:
Accelerated FPGA repair through shifted scrubbing. FPL 2013: 1-6 - 2012
- [c10]Gabriel L. Nazar, Luigi Carro:
Fast single-FPGA fault injection platform. DFT 2012: 152-157 - [c9]Fábio P. Itturriet, Ronaldo Rodrigues Ferreira, Gustavo Girão, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro:
Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-Errors. DSD 2012: 136-139 - [c8]Gabriel L. Nazar, Luigi Carro:
Fast error detection through efficient use of hardwired resources in FPGAs. ETS 2012: 1-6 - [c7]Gabriel L. Nazar, Luigi Carro:
Exploiting Modified Placement and Hardwired Resources to Provide High Reliability in FPGAs. FCCM 2012: 149-152 - [c6]Paulo C. Santos, Gabriel L. Nazar, Luigi Carro, Fakhar Anjam, Stephan Wong:
Adapting communication for adaptable processors: A multi-axis reconfiguration approach. ReConFig 2012: 1-6 - [c5]Fábio P. Itturriet, Gabriel L. Nazar, Ronaldo Rodrigues Ferreira, Álvaro F. Moreira, Luigi Carro:
Adaptive parallelism exploitation under physical and real-time constraints for resilient systems. ReCoSoC 2012: 1-8 - [c4]Fakhar Anjam, Stephan Wong, Luigi Carro, Gabriel L. Nazar, Mateus B. Rutzig:
Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor. ICSAMOS 2012: 183-192 - 2011
- [c3]Gabriel L. Nazar, Luigi Carro:
An Area Effective Parity-Based Fault Detection Technique for FPGAs. DFT 2011: 27-33 - [c2]Gabriel L. Nazar, Luigi Carro:
Energy efficient pseudo-cache architecture through fine-grained reconfigurability. ISCAS 2011: 2317-2320 - 2010
- [c1]Gabriel Luca Nazar, Christina Gimmler, Norbert Wehn:
Implementation comparisons of the QR decomposition for MIMO detection. SBCCI 2010: 210-214
Coauthor Index
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last updated on 2024-10-31 21:09 CET by the dblp team
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