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2020 – today
- 2021
[j35]Pulak Mondal
, Swapna Banerjee:
FPGA-accelerated adaptive projection-based image registration. J. Real Time Image Process. 18(1): 113-125 (2021)- 2020
- [j34]Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee:
Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology. Integr. 70: 126-137 (2020) - [j33]Pallab Kumar Nath, Swapna Banerjee:
A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process. Integr. 71: 170-182 (2020) - [j32]Biswabandhu Jana, Avishek Sinha Roy, Goutam Saha, Swapna Banerjee:
A Low-Error, Memory-Based Fast Binary Logarithmic Converter. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2129-2133 (2020) - [j31]Biswabandhu Jana, Rakesh Biswas, Pallab Kumar Nath, Goutam Saha, Swapna Banerjee:
Smartphone-Based Point-of-Care System Using Continuous-Wave Portable Doppler. IEEE Trans. Instrum. Meas. 69(10): 8352-8361 (2020)
2010 – 2019
- 2019
- [j30]Biswabandhu Jana, Kamal Oswal, Sankar Mitra, Goutam Saha, Swapna Banerjee:
Detection of peripheral arterial disease using Doppler spectrogram based expert system for Point-of-Care applications. Biomed. Signal Process. Control. 54 (2019) - [j29]Mayur Agarwal, Arijit De, Swapna Banerjee:
An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2275-2287 (2019) - [j28]Pulak Mondal, Swapna Banerjee:
A Reconfigurable Memory-Based Fast VLSI Architecture for Computation of the Histogram. IEEE Trans. Consumer Electron. 65(2): 128-133 (2019) - 2018
- [j27]Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee:
Contention free delayed keeper for high density large signal sensing memory compiler. Integr. 62: 24-33 (2018) - [j26]Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee:
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 130-140 (2018) - [j25]Praful P. Pai, Pradyut Kumar Sanki, Sudeep K. Sahoo, Arijit De, Sourangshu Bhattacharya, Swapna Banerjee:
Cloud Computing-Based Non-Invasive Glucose Monitoring for Diabetic Care. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 663-676 (2018) - [j24]Rakesh Biswas, Siddarth Reddy Malreddy, Swapna Banerjee:
A High-Precision Low-Area Unified Architecture for Lossy and Lossless 3D Multi-Level Discrete Wavelet Transform. IEEE Trans. Circuits Syst. Video Technol. 28(9): 2386-2396 (2018) - [j23]Praful P. Pai, Arijit De, Swapna Banerjee:
Accuracy Enhancement for Noninvasive Glucose Estimation Using Dual-Wavelength Photoacoustic Measurements and Kernel-Based Calibration. IEEE Trans. Instrum. Meas. 67(1): 126-136 (2018) - 2016
- [j22]Pulak Mondal, Pradyut Kumar Biswal, Swapna Banerjee:
FPGA based accelerated 3D affine transform for real-time image processing applications. Comput. Electr. Eng. 49: 69-83 (2016) - [j21]Mayur Agarwal, Arijit De, Swapna Banerjee:
Architecture of a real-time delay calculator for digital beamforming in ultrasound system. IET Circuits Devices Syst. 10(4): 322-329 (2016) - [j20]Pallab Kumar Nath, Swapna Banerjee:
A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder. Microprocess. Microsystems 40: 181-188 (2016) - [c45]Biswabandhu Jana, Swapna Banerjee:
Implementation of Smartphone Based Blood Flow Diagnoses from Doppler Spectrogram. CBMS 2016: 183-184 - [c44]Mrityunjoy Chakraborty, Sudipta Mukhopadhyay, A. Dasgupta, Swapna Banerjee, Santanu Patsa, Jay G. Ray, K. Chaudhuri:
A new paradigm of oral cancer detection using digital infrared thermal imaging. Medical Imaging: Computer-Aided Diagnosis 2016: 97853I - [i1]Ashutosh Mishra, Sudipta Mahapatra, Swapna Banerjee:
A Low Complexity VLSI Architecture for Multi-Focus Image Fusion in DCT Domain. CoRR abs/1602.07620 (2016) - 2015
- [j19]Rakesh Biswas, Kishor Sarawadekar, Srinivas Varna, Swapna Banerjee:
An FPGA-based architecture of DSC-SRI units specially for motion blind ultrasound systems. J. Real Time Image Process. 10(3): 573-595 (2015) - [j18]Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee:
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(4): 1071-1080 (2015) - [j17]Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee:
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1150-1154 (2015) - [j16]Satyabrata Sarangi, Swapna Banerjee:
Efficient Hardware Implementation of Encoder and Decoder for Golay Code. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1965-1968 (2015) - [j15]Ashutosh Mishra, Pulak Mondal, Swapna Banerjee:
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2913-2921 (2015) - [c43]Praful P. Pai, Pradyut Kumar Sanki, Arijit De, Swapna Banerjee:
NIR photoacoustic spectroscopy for non-invasive glucose measurement. EMBC 2015: 7978-7981 - [c42]Santanu Sarkar, Swapna Banerjee:
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect. ISVLSI 2015: 172-177 - [c41]Praful P. Pai, Pradyut Kumar Sanki, Swapna Banerjee:
A photoacoustics based continuous non-invasive blood glucose monitoring system. MeMeA 2015: 106-111 - 2014
- [j14]Santanu Sarkar, Swapna Banerjee:
An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters. Microelectron. J. 45(6): 666-677 (2014) - [c40]Ashutosh Mishra, Pulak Mondal, Swapna Banerjee:
2D/3D Non-rigid Image Registration by an Efficient Demons Approach. CBMS 2014: 481-482 - [c39]Satyabrata Sarangi, Praful P. Pai, Pradyut Kumar Sanki, Swapna Banerjee:
Comparative Analysis of Golay Code Based Excitation and Coherent Averaging for Non-invasive Glucose Monitoring System. CBMS 2014: 485-486 - 2013
- [j13]Pradyut Kumar Biswal, Pulak Mondal, Swapna Banerjee:
Parallel architecture for accelerating affine transform in high-speed imaging systems. J. Real Time Image Process. 8(1): 69-79 (2013) - [j12]Sounak Roy, Hiranmoy Basak, Swapna Banerjee:
Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC). Microelectron. J. 44(12): 1336-1347 (2013) - [c38]Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee:
Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter. IPDPS Workshops 2013: 247-251 - 2012
- [j11]Kishor Sarawadekar, Swapna Banerjee:
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000. Integr. 45(1): 1-8 (2012) - [j10]Kishor Sarawadekar, Harihar Bharat Indana, Deep Bera, Swapna Banerjee:
VLSI-DSP based real time solution of DSC-SRI for an ultrasound system. Microprocess. Microsystems 36(1): 1-12 (2012) - [c37]Pulak Mondal, Swapna Banerjee:
Motion estimation in medical video sequences using affine transform. CBMS 2012: 1-4 - [c36]Ashutosh Mishra, Pulak Mondal, Swapna Banerjee:
Modified Demons deformation algorithm for non-rigid image registration. IHCI 2012: 1-5 - [c35]Sounak Roy, Bibhudatta Sahoo, Swapna Banerjee:
Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid. ISCAS 2012: 2985-2988 - 2011
- [j9]Kishor Sarawadekar, Swapna Banerjee:
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000. IEEE Trans. Circuits Syst. Video Technol. 21(6): 825-836 (2011) - 2010
- [j8]Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee:
Architectural design and FPGA implementation of radix-4 CORDIC processor. Microprocess. Microsystems 34(2-4): 96-101 (2010) - [j7]Anirban Das, Anindya Hazra, Swapna Banerjee:
An Efficient Architecture for 3-D Discrete Wavelet Transform. IEEE Trans. Circuits Syst. Video Technol. 20(2): 286-296 (2010) - [c34]Vijaya Bhadauria, Krishna Kant, Swapna Banerjee:
A tunable transconductor with high linearity. APCCAS 2010: 5-8
2000 – 2009
- 2009
- [c33]Deep Bera, Leeladhar Agarwal, Swapna Banerjee:
Multirate scan conversion of ultrasound images using warped distance based adaptive bilinear interpolation. CBMS 2009: 1-5 - [c32]Kishor Sarawadekar, Swapna Banerjee:
A high speed bit plane coder for JPEG 2000 and it's FPGA implementation. EUSIPCO 2009: 2231-2234 - [c31]Kishor Sarawadekar, Swapna Banerjee:
Efficient VLSI architecture for bit plane encoder of JPEG 2000. ICIP 2009: 2805-2808 - [c30]Santanu Sarkar, Swapna Banerjee:
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. ISVLSI 2009: 268-273 - 2008
- [c29]Santanu Sarkar, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee:
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. ISCAS 2008: 149-152 - [c28]Sounak Roy, Swapna Banerjee:
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier. VLSI Design 2008: 323-329 - 2006
- [c27]Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee:
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. APCCAS 2006: 1-4 - [c26]Abhijeet Jadhav, Swapna Banerjee, P. K. Dutta, Ranjan Rashmi Paul, Mousumi Pal, P. Banerjee, K. Chaudhuri, Jyotirmoy Chatterjee:
Quantitative Analysis of Histopathological Features of Precancerous Lesion and Condition Using Image Processing Technique. CBMS 2006: 231-236 - [c25]Bodhisatwa Mazumdar, Aman Mediratta, Joydeep Bhattacharyya, Swapna Banerjee:
A Real Time Speckle Noise Cleaning Filter for Ultrasound Images. CBMS 2006: 341-346 - [c24]J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee:
Real Time Dynamic Receive Apodization for an Ultrasound Imaging System. VLSI Design 2006: 534-537 - [c23]Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee:
Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop. VLSI Design 2006: 587-592 - [c22]Sanjoy Kumar Dey, Swapna Banerjee:
An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC. VLSI Design 2006: 593-598 - 2005
- [j6]Koushik Maharatna, Swapna Banerjee, Eckhard Grass, Milos Krstic, Alfonso Troya:
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture. IEEE Trans. Circuits Syst. Video Technol. 15(11): 1463-1474 (2005) - [c21]Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee, Wouter A. Serdijn:
Design of static and dynamic translinear circuits based on CMOS CCII translinear loops. ICECS 2005: 1-4 - [c20]Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee:
A 160MSPS 8-Bit Pipeline Based ADC. VLSI Design 2005: 313-318 - [c19]Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey:
A 10-Bit 80-MSPS 2.5-V 27.65-mW 0.185-mm2 Segmented Current Steering CMOS DAC. VLSI Design 2005: 319-322 - [c18]Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee, Sriram Gupta:
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design. VLSI Design 2005: 850-853 - 2004
- [c17]Abhishek Mitra, Swapna Banerjee:
A New Interpolation Free Method for X-ray CT Image Reconstruction. CBMS 2004: 54- - [c16]Bipul Das, Swapna Banerjee:
Homogeneity Induced Inertial Snake with Application to Medical Image Segmentation. CBMS 2004: 304-309 - [c15]Anindya Hazra, J. Bhattacharyya, Swapna Banerjee:
Real Time Noise Cleaning of Ultrasound Images. CBMS 2004: 379-384 - [c14]Abhishek Mitra, Swapna Banerjee:
A regular algorithm for real time Radon & inverse Radon transform [image processing applications]. ICASSP (5) 2004: 105-108 - [c13]Koushik Maharatna, Alfonso Troya, Swapna Banerjee, Eckhard Grass, Milos Krstic:
A 16-bit CORDIC rotator for high-speed wireless LAN. PIMRC 2004: 1747-1751 - 2003
- [c12]Bipul Das, Swapna Banerjee:
A Novel Ram Architecture For Bit-Plane Based Coding. DCC 2003: 421 - [c11]Bipul Das, Swapna Banerjee:
A low complexity architecture for complex discrete wavelet transform. ICASSP (2) 2003: 309-312 - [c10]Manisha Pattanaik, Swapna Banerjee:
A New Approach to Analyze a Sub-micron CMOS Inverter. VLSI Design 2003: 116-121 - [c9]Bipul Das, Swapna Banerjee:
A Memory Efficient 3-D DWT Architecture. VLSI Design 2003: 208- - 2002
- [c8]Bipul Das, Swapna Banerjee:
A Wavelet Based Low Complexity Embedded Block Coding Algorithm. DCC 2002: 452 - [c7]B. Das, Swapna Banerjee:
VLSI architecture for a new real-time 3D wavelet transform. ICASSP 2002: 3224-3228 - [c6]Debashis Dutta, Qadeer Ahmad Khan, Swapna Banerjee:
Design of continuous-time filter for hearing aid application using current conveyors. ICECS 2002: 169-172 - 2001
- [j5]Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee:
FPGA realization of a CORDIC based FFT processor for biomedical signal processing. Microprocess. Microsystems 25(3): 131-142 (2001) - [j4]Koushik Maharatna, Swapna Banerjee:
A VLSI array architecture for Hough transform. Pattern Recognit. 34(7): 1503-1512 (2001) - [j3]Koushik Maharatna, A. S. Dhar, Swapna Banerjee:
A VLSI array architecture for realization of DFT, DHT, DCT and DST. Signal Process. 81(9): 1813-1822 (2001) - [c5]Bipul Das, Swapna Banerjee:
A CORDIC based array architecture for complex discrete wavelet transform. ACM Great Lakes Symposium on VLSI 2001: 79-84 - 2000
- [c4]Bipul Das, S. K. Mitra, Swapna Banerjee:
Knowledge Base System for Diagnostic Assessment of Doppler Spectogram. MICAI 2000: 405-416
1990 – 1999
- 1998
- [c3]Bipul Das, Swapna Banerjee:
Knowledge-based Doppler blood-velocimeter system. KES (3) 1998: 334-339 - 1995
- [j2]G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee:
Finite element analysis of SiGe heterojunction devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 803-814 (1995) - [c2]G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee:
Analysis of temperature dependence of Si-Ge HBT. VLSI Design 1995: 268-271 - 1994
- [c1]G. Hari Rama Krishna, Nirmal B. Chakrabarti, Swapna Banerjee:
Finite Element Analysis of SIGe npn HBT. VLSI Design 1994: 319-322
1970 – 1979
- 1971
- [j1]S. K. Mitra, Swapna Banerjee:
On the Probability Distribution of Round-off Errors Propagated in Tabular Differences. Aust. Comput. J. 3(2): 60-68 (1971)
Coauthor Index
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