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2020 – today
- 2024
[j6]Yuan-Chun Luo
, Anni Lu, Yandong Luo, Sou-Chi Chang, Uygar Avci, Shimeng Yu:
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1696-1703 (2024)- [j5]Yuan-Chun Luo, Anni Lu, Janak Sharda, Moritz Scherer, Jorge Tomás Gómez, Syed Shakib Sarwar, Ziyun Li, Reid Frederick Pinkham, Barbara De Salvo, Shimeng Yu:
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1718-1725 (2024) - [c10]Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu:
A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. ASPDAC 2024: 159-164 - [c9]Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu:
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. DAC 2024: 78:1-78:6 - [c8]Tae-Hyeon Kim, Yuan-Chun Luo, Omkar Phadke, James Read, Shimeng Yu:
Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read. IMW 2024: 1-4 - 2023
- [j4]Anni Lu, Jae Hur, Yuan-Chun Luo, Hai Li, Dmitri E. Nikonov, Ian A. Young, Yang-Kyu Choi, Shimeng Yu:
Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 422-435 (2023) - [c7]Omkar Phadke, Khandker Akif Aabrar, Yuan-chun Luo, Sharadindu Gopal Kirtania, Asif Islam Khan, Suman Datta, Shimeng Yu:
Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors. IRPS 2023: 1-4 - 2022
- [j3]Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu:
Nonvolatile Capacitive Crossbar Array for In-Memory Computing. Adv. Intell. Syst. 4(8) (2022) - [j2]Yandong Luo, Yuan-Chun Luo, Shimeng Yu:
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators. IEEE Trans. Computers 71(9): 2088-2101 (2022) - [j1]Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu:
Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 784-788 (2022) - 2021
- [c6]Yandong Luo, Yuan-Chun Luo, Shimeng Yu:
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training. DATE 2021: 1871-1876 - [c5]Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng:
Compute-in-Memory: From Device Innovation to 3D System Integration. ESSDERC 2021: 21-28 - [c4]Jae Hur, Yuan-Chun Luo, Zheng Wang, Wonbo Shim, Asif Islam Khan, Shimeng Yu:
A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure. IMW 2021: 1-4 - [c3]Yuan-Chun Luo, Anni Lu, Jae Hur, Shaolan Li, Shimeng Yu:
Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. IMW 2021: 1-4 - 2020
- [c2]Yuan-Chun Luo, Jae Hur, Panni Wang, Asif Islam Khan, Shimeng Yu:
Modeling Multi-states in Ferroelectric Tunnel Junction. DRC 2020: 1-2
2010 – 2019
- 2018
- [c1]Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, Cheng-Ju Lee:
DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout. VLSI-DAT 2018: 1-4
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