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ORCIDDATE 2021: Grenoble, France
- Design, Automation & Test in Europe Conference & Exhibition, DATE 2021, Grenoble, France, February 1-5, 2021. IEEE 2021, ISBN 978-3-9819263-5-4
- Valentin Egloff
, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal:
Storage Class Memory with Computing Row Buffer: A Design Space Exploration. 1-6 - José Flich, Rafael Tornero, David Rodriguez, Davide Russo, José Maria Martínez, Carles Hernández:
From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience. 7-12 - Christoph Hagleitner, Dionysios Diamantopoulos, Burkhard Ringlein, Constantinos Evangelinos, Charles R. Johns, Rong N. Chang, Bruce D'Amora, James A. Kahle, James C. Sexton, Michael Johnston, Edward Pyzer-Knapp, Chris Ward:
Heterogeneous Computing Systems for Complex Scientific Discovery Workflows. 13-18 - David Bol, Thibault Pirson, Rémi Dekimpe:
Moore's Law and ICT Innovation in the Anthropocene. 19-24 - Marc Duranton:
Few hints towards more sustainable Al. 25 - Kenshu Seto:
Scalar replacement in the presence of multiple write accesses for high-level synthesis. 26-31 - Chandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey, Ramesh Karri:
HOST: HLS Obfuscations against SMT ATtack. 32-37 - Emanuele Vitali, Davide Gadioli, Fabrizio Ferrandi, Gianluca Palermo:
Parametric Throughput Oriented Large Integer Multipliers for High Level Synthesis. 38-41 - Zi Wang, Benjamin Carrión Schäfer:
Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions. 42-45 - Qi Sun, Tinghuan Chen, Siting Liu, Jin Miao, Jianli Chen, Hao Yu, Bei Yu:
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. 46-51 - Hannah Badier, Christian Pilato, Jean-Christophe Le Lann, Philippe Coussy, Guy Gogniat:
Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis. 52-55 - Alejandro Hernández-Cane, Namiko Matsumoto, Eric Ping, Mohsen Imani:
OnlineHD: Robust, Efficient, and Single-Pass Online Learning Using Hyperdimensional System. 56-61 - Jung-Eun Kim, Richard M. Bradford, Max Del Giudice, Zhong Shao:
Adaptive Generative Modeling in Resource-Constrained Environments. 62-67 - Matthew Rowlings, Andy M. Tyrrell, Martin A. Trefzer:
Operating Beyond FPGA Tool Limitations: Nervous Systems for Embedded Runtime Management. 68-71 - Rumia Masburah, Rajib Lochan Jana, Ainuddin Khan, Shichao Xu, Shuyue Lan, Soumyajit Dey, Qi Zhu:
Adaptive Learning Based Building Load Prediction for Microgrid Economic Dispatch. 72-75 - Dimitra Nikitopoulou, Dimosthenis Masouros, Sotirios Xydis, Dimitrios Soudris:
Performance Analysis and Auto-tuning for SPARK in-memory analytics. 76-81 - Jiajia Jiao, Debjit Pal, Chenhui Deng, Zhiru Zhang:
GLAIVE: Graph Learning Assisted Instruction Vulnerability Estimation. 82-87 - Yan Li, Jun Han, Xiaoyang Zeng, Mehdi B. Tahoori:
TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications. 88-93 - Jinting Ren, Xianzhang Chen, Duo Liu, Moming Duan, Renping Liu, Chengliang Wang:
Forseti: An Efficient Basic-block-level Sensitivity Analysis Framework Towards Multi-bit Faults. 94-97 - Sanmitra Banerjee, Mahdi Nikdast, Krishnendu Chakrabarty:
Modeling Silicon-Photonic Neural Networks under Uncertainties. 98-101 - Xuanyu Huang, Rui Zhang, Yu Huang, Peiyao Wang, Mei Li:
Enhancements of Model and Method in Lithography Hotspot Identification. 102-107 - Alessio Colucci, Dávid Juhász, Martin Mosbeck, Alberto Marchisio, Semeen Rehman, Manfred Kreutzer, Günther Nadbath, Axel Jantsch, Muhammad Shafique:
MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences. 108-113 - Antonio Cipolletta, Andrea Calimera:
Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks. 114-119 - Wei Sun, Savvas Sioutas, Sander Stuijk, Andrew Nelson, Henk Corporaal:
Efficient Tensor Cores support in TVM for Low-Latency Deep learning. 120-123 - Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng:
Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. 124-129 - Boria Pérez, Alexander Fell, John D. Davis:
Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC. 130-135 - Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji:
Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. 136-141 - Gabriel H. Loh, Samuel Naffziger, Kevin Lepak:
Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. 142-145 - Gauthaman Murali, Sung Kyu Lim:
Heterogeneous 3D ICs: Current Status and Future Directions for Physical Design Technologies. 146-151 - Sanmitra Banerjee, Arjun Chaudhuri, Shao-Chun Hung, Krishnendu Chakrabarty:
Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits. 152-157 - Biresh Kumar Joardar, Aqeeb Iqbal Arka, Janardhan Rao Doppa, Partha Pratim Pande:
3D++: Unlocking the Next Generation of High-Performance and Energy-Efficient Architectures using M3D Integration. 158-163 - Kamyar Mohajerani, Richard Haeussler, Rishub Nagpal, Farnoud Farahmand, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj:
Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process. 164-169 - Andrea Caforio, Fatih Balli, Subhadeep Banik, Francesco Regazzoni:
A Deeper Look at the Energy Consumption of Lightweight Block Ciphers. 170-175 - Anubhab Baksi, Jakub Breier, Yi Chen, Xiaoyang Dong:
Machine Learning Assisted Differential Distinguishers For Lightweight Ciphers. 176-181 - Xiaolu Hou, Jakub Breier, Shivam Bhasin:
DNFA: Differential No-Fault Analysis of Bit Permutation Based Ciphers Assisted by Side-Channel. 182-187 - Stefan Hillmich, Richard Kueng, Igor L. Markov, Robert Wille:
As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation. 188-193 - Thomas Grurl, Richard Kueng, Jürgen Fuß, Robert Wille:
Stochastic Quantum Circuit Simulation Using Decision Diagrams. 194-199 - Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler:
Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures. 200-205 - Raviv Gal, Eldad Haber, Wesam Ibraheem, Brian Irwin, Ziv Nevo, Avi Ziv:
Automatic Scalable System for the Coverage-Directed Generation (CDG) Problem. 206-211 - Tom Kolan, Hillel Mendelson, Vitali Sokhin, Shai Doron, Hernan Theiler, Shay Aviv, Hagai Hadad, Natalia Freidman, Elena Tsanko, John M. Ludden, Bryant Cockcroft:
Post Silicon Validation of the MMU. 212-217 - Sören Tempel, Vladimir Herdt, Rolf Drechsler:
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. 218-221 - Stefano Aldegheri, Nicola Bombieri, Samuele Germiniani, Federico Moschin, Graziano Pravadelli:
A containerized ROS-compliant verification environment for robotic systems. 222-225 - Paulo C. Santos, Bruno E. Forlin, Luigi Carro:
Sim2PIM: A Fast Method for Simulating Host Independent & PIM Agnostic Designs. 226-231 - Sven Thijssen, Sumit Kumar Jha, Rickard Ewetz:
COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter. 232-237 - Jiaqi Gu, Chenghao Feng, Zheng Zhao, Zhoufeng Ying, Mingjie Liu, Ray T. Chen, David Z. Pan:
SqueezeLight: Towards Scalable Optical Neural Networks with Multi-Operand Ring Resonators. 238-243 - Yingxun Fu, Xun Liu, Jiwu Shu, Zhirong Shen, Shiye Zhang, Jun Wu, Li Ma:
Receptive-Field and Switch-Matrices Based ReRAM Accelerator with Low Digital-Analog Conversion for CNNs. 244-247 - Yiwen Geng, Bin Gao, Qingtian Zhang, Wenqiang Zhang, Peng Yao, Yue Xi, Yudeng Lin, Junren Chen, Jianshi Tang, Huaqiang Wu, He Qian:
An On-chip Layer-wise Training Method for RRAM based Computing-in-memory Chips. 248-251 - Sarah Azimi, Corrado De Sio, Luca Sterpone:
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor. 252-257 - Yue Tang, Nan Guan, Zhiwei Feng, Xu Jiang, Wang Yi:
Response Time Analysis of Lazy Round Robin. 258-263 - Behnaz Ranjbar, Ali Hoseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar:
Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem. 264-269 - Waqar Ali, Rodolfo Pellizzoni, Heechul Yun:
Virtual Gang Scheduling of Parallel Real-Time Tasks. 270-275 - Dejan S. Milojicic, Paolo Faraboschi, Nicolas Dubé, Duncan Roweth:
Future of HPC: Diversifying Heterogeneity. 276-281 - Yijia Zhang, Daniel Curtis Wilson, Ioannis Ch. Paschalidis, Ayse K. Coskun:
A Data Center Demand Response Policy for Real-World Workload Scenarios in HPC. 282-287 - John Glassmire, Hamideh Bitaraf, Stylianos Papadakis, Alexandre Oudalov:
Accelerating data center decarbonization and maximizing renewable usage with grid edge solutions. 288-293 - Rémi Bouzel, Yanik Ngoko, Paul Benoit, Nicolas Sainthérant:
Distributed Grid computing Manager covering Waste Heat Reuse Constraints. 294-299 - Mikail Yayla, Kuan-Hsun Chen, Georgios Zervakis, Jörg Henkel, Jian-Jia Chen, Hussam Amrouch:
FeFET and NCFET for Future Neural Networks: Visions and Opportunities. 300-305 - Dayane Reis, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu:
Exploiting FeFETs via Cross-Layer Design from In-memory Computing Circuits to Meta-Learning Applications. 306-311 - Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo:
Future Computing Platform Design: A Cross-Layer Design Approach. 312-317 - Onur Mutlu:
Intelligent Architectures for Intelligent Computing Systems. 318-323 - Mahmoud Elfar, Tung-Che Liang, Krishnendu Chakrabarty, Miroslav Pajic:
Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips. 324-329 - Minxuan Zhou, Muzhou Li, Mohsen Imani, Tajana Rosing:
HyGraph: Accelerating Graph Processing with Hybrid Memory-centric Computing. 330-335 - Sudip Poddar, Gerold Fink, Werner Haselmayr, Robert Wille:
Generic Sample Preparation for Different Microfluidic Platforms. 336-339 - Fan Chen, Linghao Song, Hai Helen Li, Yiran Chen:
RAISE: A Resistive Accelerator for Subject-Independent EEG Signal Classification. 340-343 - Oliver Keszöcze, Naser Mohammadzadeh, Robert Wille:
Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures. 344-349 - Fang-Chi Wu, Jian-De Li, Katherine Shu-Min Li, Sying-Jyan Wang, Tsung-Yi Ho:
Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips. 350-353 - Shubham Rai, Heinz Riener, Giovanni De Micheli, Akash Kumar:
Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies. 354-359 - Anna Bernasconi, Valentina Ciriani:
Autosymmetry of Incompletely Specified Functions. 360-365 - Alex Chan, Danil Sokolov, Victor Khomenko, David Lloyd, Alex Yakovlev:
Synthesis of SI Circuits from Burst-Mode Specifications. 366-369 - Adrian Wheeldon, Alex Yakovlev, Rishad A. Shafik, Jordan Morris:
Low-Latency Asynchronous Logic Design for Inference at the Edge. 370-373 - Weihua Xiao, Weikang Qian, Weiqiang Liu:
GOMIL: Global Optimization of Multiplier by Integer Linear Programming. 374-379 - Christoph Beyerstedt, Jonas Meier, Fabian Speicher, Ralf Wunderlich, Stefan Heinen:
An Event-Driven System-Level Noise Analysis Methodology for RF Systems. 380-385 - K. Gaurav Kumar, Baibhab Chatterjee, Shreyas Sen:
OpenSerDes: An Open Source Process-Portable All-Digital Serial Link. 386-391 - Wenhao Wang, Yukui Luo, Xiaolin Xu:
Constructive Use of Process Variations: Reconfigurable and High-Resolution Delay-Line. 392-395 - Thibault Vayssade, Florence Azaïs, Laurent Latorre, François Lefèvre:
Digital test of ZigBee transmitters: Validation in industrial test environment. 396-401 - Mengyuan Li, Xiaobo Sharon Hu:
A Quantization Framework for Neural Network Adaption at the Edge. 402-407 - Behnam Khaleghi, Hanyang Xu, Justin Morris, Tajana Simunic Rosing:
tiny-HD: Ultra-Efficient Hyperdimensional Computing Engine for IoT Applications. 408-413 - Zeinab Hakimi, Vijaykrishnan Narayanan:
Resolution-Aware Deep Multi-View Camera Systems. 414-417 - Xiangzhong Luo, Di Liu, Shuo Huai, Weichen Liu:
HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture Search. 418-421 - Ziyi Guan, Shuwei Li, Yuan Cheng, Changhai Man, Wei Mao, Ngai Wong, Hao Yu:
A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices. 422-427 - Charles Steinmetz, Greyce N. Schroeder, Achim Rettberg, Ricardo Nagel Rodrigues, Carlos Eduardo Pereira:
Enabling and supporting car-as-a-service by digital twin modeling and deployment. 428-433 - Khaled Alamin, Sara Vinco, Massimo Poncino, Nicola Dall'Ora, Enrico Fraccaroli, Davide Quaglia:
Digital Twin Extension with Extra-Functional Properties. 434-439 - Mohammad Abdullah Al Faruque, Deepan Muthirayan, Shih-Yuan Yu, Pramod P. Khargonekar:
Cognitive Digital Twin for Manufacturing Systems. 440-445 - Thomas Markwirth, Roland Jancke, Christoph Sohrmann:
Dynamic fault injection into digital twins of safety-critical systems. 446-450 - Markus Gutmann, Bernhard Rinner:
Mission Specification and Execution of Multidrone Systems. 451-456 - Clara Hobbs, Debayan Roy, Parasara Sridhar Duggirala, F. Donelson Smith, Soheil Samii, James H. Anderson, Samarjit Chakraborty:
Perception Computing-Aware Controller Synthesis for Autonomous Systems. 457-462 - Kruttidipta Samal, Marilyn Wolf, Saibal Mukhopadhyay:
Closed-loop Approach to Perception in Autonomous System. 463-468 - Xinkai Zhang, Justin M. Bradley:
Computing for Control and Control for Computing. 469-474 - Sohan Lal, Jan Lucas, Ben H. H. Juurlink:
QSLC: Quantization-Based, Low-Error Selective Approximation for GPUs. 475-480 - Younghoon Kim, Swagath Venkataramani, Sanchari Sen, Anand Raghunathan:
Value Similarity Extensions for Approximate Computing in General-Purpose Processors. 481-486 - Ricardo Garcia, Fatemeh Asgarinejad, Behnam Khaleghi, Tajana Rosing, Mohsen Imani:
TruLook: A Framework for Configurable GPU Approximation. 487-490 - Isaías B. Felzmann, João Fabrício Filho, Lucas Francisco Wanner:
AxPIKE: Instruction-level Injection and Evaluation of Approximate Computing. 491-494 - Bo Liu, Zeyu Shen, Lepeng Huang, Yu Gong, Zilong Zhang, Hao Cai:
A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition. 495-500 - Haiyang Pan, Yuhang Liu, Tianyue Lu, Mingyu Chen:
LSP: Collective Cross-Page Prefetching for NVM. 501-506 - Yifu Deng, Jianhui Yue, Zhiyuan Lu, Yifeng Zhu:
Efficient Hardware-assisted Out-place Update for Persistent Memory. 507-512 - Zejian Liu, Gang Li, Jian Cheng:
Hardware Acceleration of Fully Quantized BERT for Efficient Natural Language Processing. 513-516 - Seyed Saber Nabavi Larimi, Behzad Salami, Osman S. Unsal, Adrián Cristal Kestelman, Hamid Sarbazi-Azad, Onur Mutlu:
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling. 517-522 - Haitao Meng, Chonghao Zhong, Jianfeng Gu, Gang Chen:
A GPU -accelerated Deep Stereo- LiDAR Fusion for Real-time High-precision Dense Depth Sensing. 523-528 - Mohammad Hamad, Emanuel Regnath, Jan Lauinger, Vassilis Prevelakis, Sebastian Steinhorst:
SPPS: Secure Policy-based Publish/Subscribe System for V2C Communication. 529-534 - Daichi Watari, Ittetsu Taniguchi, Francky Catthoor, Charalampos Marantos, Kostas Siozios, Elham Shirazi, Dimitrios Soudris, Takao Onoye:
Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building. 535-538 - Jonas Peeck, Johannes Schlatow, Rolf Ernst:
Online latency monitoring of time-sensitive event chains in safety-critical applications. 539-542 - Wei Zhang, Songran Liu, Mingsong Lv, Qiulin Chen, Nan Guan:
Intermittent Computing with Efficient State Backup by Asynchronous DMA. 543-548 - Cezar Reinbrecht, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil, Johanna Sepúlveda:
GRINCH: A Cache Attack against GIFT Lightweight Cipher. 549-554 - Melissa Azouaoui, Kostas Papagiannopoulos, Dominik Zürner:
Blind Side-Channel SIFA. 555-560 - Anubhab Baksi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay, Vinay B. Y. Kumar:
Feeding Three Birds With One Scone: A Generic Duplication Based Countermeasure To Fault Attacks. 561-564 - David Pokorný, Petr Socha, Martin Novotný:
Side-channel attack on Rainbow post-quantum signature. 565-568 - Muhtadi Choudhury, Domenic Forte, Shahin Tajik:
PATRON: A Pragmatic Approach for Encoding Laser Fault Injection Resistant FSMs. 569-574 - Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu:
An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. 575-580 - Wachirawit Ponghiran, Kaushik Roy:
Hybrid Analog-Spiking Long Short-Term Memory for Energy Efficient Computing on Edge Devices. 581-586 - Dehua Liang, Masanori Hashimoto, Hiromitsu Awano:
BloomCA: A Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter. 587-590 - Jung-Eun Kim, Richard M. Bradford, Max Del Giudice, Zhong Shao:
Paired Training Framework for Time-Constrained Learning. 591-596 - Sukhan Lee, Soojin Lee:
Machine Learning Based Real-Time Industrial Bin-Picking: Hybrid and Deep Learning Approaches. 597-602 - Davide Cannizzaro, Antonio Giuseppe Varrella, Stefano Paradiso, Roberta Sampieri, Enrico Macii, Edoardo Patti, Santa Di Cataldo:
Image analytics and machine learning for in-situ defects detection in Additive Manufacturing. 603-608 - Zijie Ren, Jiafu Wan:
Strengthening Digital Twin Applications based on Machine Learning for Complex Equipment. 609-614 - Florian Fricke, Safdar Mahmood, Javier Hoffmann, Marcelo Brandalero, Sascha Liehr, Simon Kern, Klas Meyer, Stefan Kowarik, Stephan Westerdick, Michael Maiwald, Michael Hübner:
Artificial Intelligence for Mass Spectrometry and Nuclear Magnetic Resonance Spectroscopy. 615-620 - Amine Jaamoum, Thomas Hiscock, Giorgio Di Natale:
Scramble Cache: An Efficient Cache Architecture for Randomized Set Permutation. 621-626 - Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser:
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. 627-632 - Sarani Bhattacharya, Ingrid Verbauwhede:
Exploring Micro-architectural Side-Channel Leakages through Statistical Testing. 633-636 - Vishal Gupta, Vinod Ganesan, Biswabandan Panda:
Seclusive Cache Hierarchy for Mitigating Cross-Core Cache and Coherence Directory Attacks. 637-640 - Ivan De Oliveira Nunes, Sashidhar Jakkamsetti, Gene Tsudik:
Tiny-CFA: Minimalistic Control-Flow Attestation Using Verified Proofs of Execution. 641-646 - Marouene Boubakri, Fausto Chiatante, Belhassen Zouari:
Towards a firmware TPM on RISC-V. 647-650 - Surya Selvam, Vinod Ganesan, Pratyush Kumar:
FuSeConv: Fully Separable Convolutions for Fast Inference on Systolic Arrays. 651-656 - Rui Xu, Sheng Ma, Yaohua Wang, Yang Guo:
HeSA: Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators. 657-662 - Sungju Ryu, Youngtaek Oh, Taesu Kim, Daehyun Ahn, Jae-Joon Kim:
SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching. 663-666 - Jingyao Zhang, Huaxi Gu, Grace Li Zhang, Bing Li, Ulf Schlichtmann:
Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs. 667-672 - Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler, Mikail Yayla:
Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance. 673-678 - Cecilia De la Parra, Xuyi Wu, Andre Guntoro, Akash Kumar:
Knowledge Distillation and Gradient Estimation for Active Error Compensation in Approximate Neural Networks. 679-684 - Dimitrios Stathis, Yu Yang, Ahmed Hemani, Anders Lansner:
Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex. 685-688 - Tianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta:
GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks. 689-694 - Kousik Kumar Dutta, Prathamesh Nitin Tanksale, Shirshendu Das:
A Fairness Conscious Cache Replacement Policy for Last Level Cache. 695-700 - Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini:
MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. 701-706 - Quentin Huppert, Timon Evenblij, Manu Perumkunnil, Francky Catthoor, Lionel Torres, David Novo:
Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation. 707-710 - Ramon Canal, Yiannakis Sazeides, Arkady Bramnik:
SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays. 711-716 - Marc Benito, Matina Maria Trompouki, Leonidas Kosmidis, Juan David Garcia, Sergio Carretero, Ken Wenger:
Comparison of GPU Computing Methodologies for Safety-Critical Systems: An Avionics Case Study. 717-718 - Matias Vara Larsen:
Verifying the Conformance of a Driver Implementation to the VirtIO Specification. 719-720 - Youngbog Yoon, Daeyong Han, Shinho Chu, Sangho Lee, Jaeduk Han, Junhyun Chun:
Process-Portable and Programmable Layout Generation of Digital Circuits in Advanced DRAM Technologies. 721-722 - Justin Morris, Kazim Ergun, Behnam Khaleghi, Mohsen Imani, Baris Aksanli, Tajana Rosing:
HyDREA: Towards More Robust and Efficient Machine Learning Systems with Hyperdimensional Computing. 723-728 - Muhammad Abdullah Hanif, Muhammad Shafique:
DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On-Chip Weight Memories in Deep Neural Network Hardware Architectures. 729-734 - Jaehun Jang, Jong Hwan Ko:
WISER: Deep Neural Network Weight-bit Inversion for State Error Reduction in MLC NAND Flash. 735-738 - Bo Dong, Zheng Wang, Wenxuan Chen, Chao Chen, Yongkui Yang, Zhibin Yu:
OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic Redundancy. 739-742 - Theofilos Spyrou, Sarah A. El-Sayed, Engin Afacan, Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Haralampos-G. Stratigopoulos:
Neuron Fault Tolerance in Spiking Neural Networks. 743-748 - Kai-Björn Gemlau, Leonie Köhler, Rolf Ernst:
Efficient Run-Time Environments for System-Level LET Programming. 749-754 - Birgit Vogel-Heuser, Juliane Fischer, Dieter Hess, Eva-Maria Neumann, Marcus Würr:
Managing Variability and Reuse of Extra-functional Control Software in CPPS. 755-760 - Miguel Fernando Gonzalez-Zalba:
Quantum computing with CMOS technology. 761 - Carmen G. Almudéver, Eduard Alarcón:
Structured Optimized Architecting of Full-Stack Quantum Systems in the NISQ era. 762-767 - Robert Wille, Lukas Burgholzer, Michael Artner:
Visualizing Decision Diagrams for Quantum Computing (Special Session Summary). 768-773 - Rida El-Allami, Alberto Marchisio, Muhammad Shafique, Ihsen Alouani:
Securing Deep Spiking Neural Networks against Adversarial Attacks through Inherent Structural Parameters. 774-779 - Lilas Alrahis, Satwik Patnaik, Faiq Khalid, Muhammad Abdullah Hanif, Hani H. Saleh, Muhammad Shafique, Ozgur Sinanoglu:
GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking. 780-785 - Xianglong Feng, Mengmei Ye, Ke Xia, Sheng Wei:
Runtime Fault Injection Detection for FPGA-based DNN Execution Using Siamese Path Verification. 786-789 - Jingtao Li, Adnan Siraj Rakin, Zhezhi He, Deliang Fan, Chaitali Chakrabarti:
RADAR: Run-time Adversarial Weight Attack Detection and Accuracy Recovery. 790-795 - Li Liu, Ke Zhou:
PTierDB: Building Better Read-Write Cost Balanced Key-Value Stores for Small Data on SSD. 796-801 - Qiulin Wu, You Zhou, Fei Wu, Ke Wang, Hao Lv, Jiguang Wan, Changsheng Xie:
SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead Logging. 802-807 - Lihua Yang, Zhipeng Tan, Fang Wang, Shiyun Tu, Jicheng Shao:
M2H: Optimizing F2FS via Multi-log Delayed Writing and Modified Segment Cleaning based on Dynamically Identified Hotness. 808-811 - Abdelrahman Hosny, Sherief Reda:
Characterizing and Optimizing EDA Flows for the Cloud. 812-815 - Anirudh Mohan Kaushik, Hiren D. Patel:
Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols. 816-821 - Sahand Salamat, Jaeyoung Kang, Yeseong Kim, Mohsen Imani, Niema Moshiri, Tajana Rosing:
FPGA Acceleration of Protein Back-Translation and Alignment. 822-827 - Maria Rafaela Gkeka, Alexandros Patras, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas:
FPGA Architectures for Approximate Dense SLAM Computing. 828-833 - Haichang Yang, Zhaoshi Li, Jiawei Wang, Shouyi Yin, Shaojun Wei, Leibo Liu:
HeteroKV: A Scalable Line-rate Key-Value Store on Heterogeneous CPU-FPGA Platforms. 834-837 - Takashi Imagawa, Jaehoon Yu, Masanori Hashimoto, Hiroyuki Ochi:
MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. 838-843 - Haojun Xia, Lei Gong, Chao Wang, Xianglan Chen, Xuehai Zhou:
LAP: A Lightweight Automata Processor for Pattern Matching Tasks. 844-849 - Zhuowen Zou, Yeseong Kim, M. Hassan Najafi, Mohsen Imani:
ManiHD: Efficient Hyper-Dimensional Learning Using Manifold Trainable Encoder. 850-855 - Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim:
Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. 856-861 - Yu Bai, Omair Rafique, Klaus Schneider:
A Model-based Design Flow for Asynchronous Implementations from Synchronous Specifications. 862-867 - Songran Liu, Wei Zhang, Mingsong Lv, Qiulin Chen, Nan Guan:
Surviving Transient Power Failures with SRAM Data Retention. 868-873 - Robert Balas, Luca Benini:
RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis. 874-877 - Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Giuseppe Tagliavini, Andrea Acquaviva:
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers. 878-883 - Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda:
Efficiency-driven Hardware Optimization for Adversarially Robust Neural Networks. 884-889 - Shamma Nasrin, Priyesh Shukla, Shruthi Jaisimha, Amit Ranjan Trivedi:
Compute-in-Memory Upside Down: A Learning Operator Co-Design Perspective for Scalability. 890-895 - Minah Lee, Xueyuan She, Biswadeep Chakraborty, Saurabh Dash, Burhan Ahmad Mudassar, Saibal Mukhopadhyay:
Reliable Edge Intelligence in Unreliable Environment. 896-901 - Nitin Rathi, Amogh Agrawal, Chankyu Lee, Adarsh Kumar Kosta, Kaushik Roy:
Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives. 902-907 - Sina Asadi, M. Hassan Najafi, Mohsen Imani:
A Low-Cost FSM-based Bit-Stream Generator for Low-Discrepancy Stochastic Computing. 908-913 - Dennis D. Weller, Nathaniel Bleier, Michael Hefenbrock, Jasmin Aghassi-Hagmann, Michael Beigl, Rakesh Kumar, Mehdi B. Tahoori:
Printed Stochastic Computing Neural Networks. 914-919 - Dongning Ma, Rahul Thapa, Xingjian Wang, Xun Jiao, Cong Hao:
Workload-Aware Approximate Computing Configuration. 920-925 - Geng Yuan, Payman Behnam, Yuxuan Cai, Ali Shafiee, Jingyan Fu, Zhiheng Liao, Zhengang Li, Xiaolong Ma, Jieren Deng, Jinhui Wang, Mahdi Nazm Bojnordi, Yanzhi Wang, Caiwen Ding:
TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators. 926-931 - Anni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu:
A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator. 932-937 - Avilash Mukherjee, Kumar Saurav, Prashant J. Nair, Sudip Shekhar, Mieszko Lis:
A Case for Emerging Memories in DNN Accelerators. 938-941 - Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, Bo Zhang, Jian Meng, Mingoo Seok, Jae-Sun Seo:
Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. 942-947 - Abdulqader Nael Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotofana, Florin Ciubotaru, Said Hamdioui:
Fan-out of 2 Triangle Shape Spin Wave Logic Gates. 948-953 - Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin:
Towards AQFP-Capable Physical Design Automation. 954-959 - Xuecui Zou, Sally Ahmed, Hossein Fariborzi:
Implementation of A MEMS Resonator-based Digital to Frequency Converter Using Artificial Neural Networks. 960-963 - Bruno Schmitt, Ali Javadi-Abhari, Giovanni De Micheli:
Compilation flow for classically defined quantum operations. 964-967 - Rohith Acharya, Fahd A. Mohiyaddin, Anton Potocnik, Kristiaan De Greve, Bogdan Govoreanu, Iuliana P. Radu, Georges G. E. Gielen, Francky Catthoor:
Circuit models for the co-simulation of superconducting quantum computing systems. 968-973 - Robert Wille, Tom Peham, Judith Przigoda, Nils Przigoda:
Towards Automatic Design and Verification for Level 3 of the European Train Control System. 974-979 - Abdoulaye Gamatié, Gilles Sassatelli, Marius Mikucionis:
Modeling and Analysis for Energy-Driven Computing using Statistical Model-Checking. 980-985 - Zhaorui Wu, Yuhui Deng, Hao Feng, Yi Zhou, Geyong Min:
Blender: A Traffic-Aware Container Placement for Containerized Data Centers. 986-989 - Jiaqi Yin, Huibiao Zhu, Yuan Fei:
SC4MEC: Automated Implementation of A Secure Hierarchical Calculus for Mobile Edge Computing. 990-993 - Oumaima Matoussi:
NoC Performance Model for Efficient Network Latency Estimation. 994-999 - Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi:
Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks. 1000-1005 - Arnold Abromeit, Florian Bache, Leon A. Becker, Marc Gourjon, Tim Güneysu, Sabrina Jorn, Amir Moradi, Maximilian Orlt, Falk Schellenberg:
Automated Masking of Software Implementations on Industrial Microcontrollers. 1006-1011 - Dennis R. E. Gnad, Vincent Meyers, Nguyen Minh Dang, Falk Schellenberg, Amir Moradi, Mehdi B. Tahoori:
Stealthy Logic Misuse for Power Analysis Attacks in Multi-Tenant FPGAs. 1012-1015 - Dong-Hyun Seo, Mayukh Nath, Debayan Das, Santosh Ghosh, Shreyas Sen:
Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry Sensing. 1016-1019 - Ferhat Yaman, Ahmet Can Mert, Erdinç Öztürk, Erkay Savas:
A Hardware Accelerator for Polynomial Multiplication Operation of CRYSTALS-KYBER PQC Scheme. 1020-1025 - Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. 1026-1031 - Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita:
Logic Synthesis for Generalization and Learning Addition. 1032-1037 - Hitarth Kanakia, Mahdi Nazemi, Arash Fayyazi, Massoud Pedram:
ESPRESSO-GPU: Blazingly Fast Two-Level Logic Minimization. 1038-1043 - Bruno Schmitt, Fereshte Mozafari, Giulia Meuli, Heinz Riener, Giovanni De Micheli:
From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++. 1044-1049 - Mathias Soeken, Mariia Mykhailova, Vadym Kliuchnikov, Christopher E. Granade, Alexander Vaschillo:
A Resource Estimation and Verification Workflow in Q# Special session paper. 1050-1055 - Damien Nguyen, Dmitry Mikushin, Yung Man Hong:
HiQ-ProjectQ: Towards user-friendly and high-performance quantum computing on GPUs. 1056-1061 - Jiaqi Gu, Zheng Zhao, Chenghao Feng, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
O2NN: Optical Neural Networks with Differential Detection-Enabled Optical Operands. 1062-1067 - Grace Li Zhang, Bing Li, Xing Huang, Chen Shen, Shuhang Zhang, Florin Burcea, Helmut Graeb, Tsung-Yi Ho, Hai Li, Ulf Schlichtmann:
An Efficient Programming Framework for Memristor-based Neuromorphic Computing. 1068-1073 - Ching-Yuan Chen, Krishnendu Chakrabarty:
Efficient Identification of Critical Faults in Memristor Crossbars for Deep Neural Networks. 1074-1077 - Ziqi Meng, Weikang Qian, Yilong Zhao, Yanan Sun, Rui Yang, Li Jiang:
Digital Offset for RRAM-based Neuromorphic Computing: A Novel Solution to Conquer Cycle-to-cycle Variation. 1078-1083 - Arman Kazemi, Mohammad Mehdi Sharifi, Ann Franchesca Laguna, Franz Müller, Ramin Rajaei, Ricardo Olivo, Thomas Kämpfe, Michael T. Niemier, X. Sharon Hu:
In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories. 1084-1089 - Yu Qian, Zhenhao Fan, Haoran Wang, Chao Li, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin:
Energy-Aware Designs of Ferroelectric Ternary Content Addressable Memory. 1090-1095 - Mingwang Zhao, Jun Li, Zhigang Cai, Jianwei Liao, Yuanquan Shi:
Block Attribute-aware Data Reallocation to Alleviate Read Disturb in SSDs. 1096-1099 - Hongtao Zhong, Shengjie Cao, Huazhong Yang, Xueqing Li:
Dynamic Ternary Content-Addressable Memory Is Indeed Promising: Design and Benchmarking Using Nanoelectromechanical Relays. 1100-1103 - Wei Zhao, Wei Tong, Dan Feng, Jingning Liu, Zhangyu Chen, Jie Xu, Bing Wu, Chengning Wang, Bo Liu:
Improving the energy efficiency of STT-MRAM based approximate cache. 1104-1109 - Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. 1110-1115 - Karsten Scheibler, Felix Winterer, Tobias Seufert, Tino Teige, Christoph Scholl, Bernd Becker:
ICP and IC3. 1116-1121 - Gianpiero Cabodi, Paolo E. Camurati, Alexey Ignatiev, João Marques-Silva, Marco Palena, Paolo Pasini:
Optimizing Binary Decision Diagrams for Interpretable Machine Learning Classification. 1122-1125 - Muhammad Monir Hossain, Farimah Farahmandi, Mark M. Tehranipoor, Fahim Rahman:
BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking. 1126-1129 - Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik:
Leveraging Processor Modeling and Verification for General Hardware Modules. 1130-1135 - Reza Mirosanlou, Mohamed Hassan, Rodolfo Pellizzoni:
Duetto: Latency Guarantees at Minimal Performance Cost. 1136-1141 - Nathan Liu, Carlos Moreno, Murray Dunne, Sebastian Fischmeister:
vProfile: Voltage-Based Anomaly Detection in Controller Area Networks. 1142-1147 - Saeid Dehnavi, Dip Goswami, Martijn Koedam, Andrew Nelson, Kees Goossens:
Modeling, implementation, and analysis of XRCE-DDS applications in distributed multi-processor real-time embedded systems. 1148-1151 - Maxim Mattheeuws, Björn Forsberg, Andreas Kurth, Luca Benini:
Analyzing Memory Interference of FPGA Accelerators on Multicore Hosts in Heterogeneous Reconfigurable SoCs. 1152-1155 - Ohchul Kwon, Gero Schwäricke, Tomasz Kloda, Denis Hoornaert, Giovani Gracioli, Marco Caccamo:
Flexible Cache Partitioning for Multi-Mode Real-Time Systems. 1156-1161 - Roger Pujol, Hamid Tabani, Jaume Abella, Mohamed Hassan, Francisco J. Cazorla:
Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence. 1162-1165 - Nimisha Limaye, Satwik Patnaik, Ozgur Sinanoglu:
Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques. 1166-1171 - Rakibul Hassan, Gaurav Kolhe, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao:
A Cognitive SAT to SAT-Hard Clause Translation-based Logic Obfuscation. 1172-1177 - Amin Rezaei, Hai Zhou:
Sequential Logic Encryption Against Model Checking Attack. 1178-1181 - Yinghua Hu, Kaixin Yang, Subhajit Dutta Chowdhury, Pierluigi Nuzzo:
Risk-Aware Cost-Effective Design Methodology for Integrated Circuit Locking. 1182-1185 - Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai:
Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. 1186-1191 - Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele:
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction. 1192-1197 - Jinghan Zhang, Aly Sultan, Hamed Tabkhi, Gunar Schirner:
MG-DmDSE: Multi-Granularity Domain Design Space Exploration Considering Function Similarity. 1198-1203 - Rodolfo Jordão, Ingo Sander, Matthias Becker:
Formulation of Design Space Exploration Problems by Composable Design Space Identification. 1204-1207 - Eiji Yoshiya, Tomoya Nakanishi, Tsuyoshi Isshiki:
RTL Design Framework for Embedded Processor by using C++ Description. 1208-1211 - Debashis Ganguly, Rami G. Melhem, Jun Yang:
An Adaptive Framework for Oversubscription Management in CPU-GPU Unified Memory. 1212-1217 - Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou:
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. 1218-1223 - Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar:
Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. 1224-1229 - Shengqi Yu, Rishad A. Shafik, Thanasin Bunnam, Kaiyun Chen, Alex Yakovlev:
Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier Design. 1230-1233 - Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani:
Analog Layout Generation using Optimized Primitives. 1234-1239 - Fan Chen, Linghao Song, Hai Li, Yiran Chen:
Marvel: A Vertical Resistive Accelerator for Low-Power Deep Learning Inference in Monolithic 3D. 1240-1245 - Yenai Ma, Leila Delshadtehrani, Cansu Demirkiran, José L. Abellán, Ajay Joshi:
TAP-2.5D: A Thermally-Aware Chiplet Placement Methodology for 2.5D Systems. 1246-1251 - Youngmoon Lee:
Thermal-Aware Design and Management of Embedded Real-Time Systems. 1252-1255 - Mohsen Seyedkazemi Ardebili, Marcello Zanghieri, Alessio Burrello, Francesco Beneventi, Andrea Acquaviva, Luca Benini, Andrea Bartolini:
Prediction of Thermal Hazards in a Real Datacenter Room Using Temporal Convolutional Networks. 1256-1259 - Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto:
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. 1260-1265 - Jianqi Chen, Benjamin Carrión Schäfer:
Watermarking of Behavioral IPs: A Practical Approach. 1266-1271 - Hao Cheng, Johann Großschädl, Peter B. Rønne, Peter Y. A. Ryan:
AVRNTRU: Lightweight NTRU-based Post-Quantum Cryptography for 8-bit AVR Microcontrollers. 1272-1277 - Leila Delshadtehrani, Sadullah Canakci, Manuel Egele, Ajay Joshi:
SealPK: Sealable Protection Keys for RISC-V. 1278-1281 - Eduardo Chielle, Homer Gamil, Michail Maniatakos:
Real-time Private Membership Test using Homomorphic Encryption. 1282-1287 - Tobias Kain, Hans Tompits, Timo Frederik Horeis, Johannes Heinrich, Julian-Steffen Müller, Fabian Plinke, Hendrik Decke, Marcel Aguirre Mehlhorn:
C-PO: A Context-Based Application-Placement Optimization for Autonomous Vehicles. 1288-1293 - Philipp Weiss, Sherif Elsabbahy, Andreas Weichslgartner, Sebastian Steinhorst:
Worst-Case Failover Timing Analysis of Distributed Fail-Operational Automotive Applications. 1294-1299 - Laurin Prenzel, Sebastian Steinhorst:
Decentralized Autonomous Architecture for Resilient Cyber-Physical Production Systems. 1300-1303 - Florian Ziesche, Verena Klös, Sabine Glesner:
Anomaly Detection and Classification to enable Self-Explainability of Autonomous Systems. 1304-1309 - Chih-Hong Cheng:
Provably-Robust Runtime Monitoring of Neuron Activation Patterns. 1310-1313 - Leonidas Kosmidis, Iván Rodriguez, Alvaro Jover-Alvarez, Sergi Alcaide, Jérôme Lachaize, Olivier Notebaert, Antoine Certain, David Steenari:
GPU4S: Major Project Outcomes, Lessons Learnt and Way Forward. 1314-1319 - Christian Pilato, Stanislav Böhm, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Vojtech Cima, Radim Cmar, Dionysios Diamantopoulos, Fabrizio Ferrandi, Jan Martinovic, Gianluca Palermo, Michele Paolino, Antonio Parodi, Lorenzo Pittaluga, Daniel Raho, Francesco Regazzoni, Katerina Slaninová, Christoph Hagleitner:
EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms. 1320-1325 - Thomas Strathmann, Georg Hake, Houssem Guissouma, Carl Philipp Hohl, Yosab Bebawy, Sebastian Vander Maelen, Andrew Koerner:
Project Overview for Step-Up!CPS - Process, Methods and Technologies for Updating Safety-critical Cyber-physical Systems. 1326-1329 - Andrey Sadovykh, Gunnar Widforss, Dragos Truscan, Eduard Paul Enoiu, Wissam Mallouli, Rosa Iglesias, Alessandra Bagnato, Olga Hendel:
VeriDevOps: Automated Protection and Prevention to Meet Security Requirements in DevOps. 1330-1333 - Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer:
Nano Security: From Nano-Electronics to Secure Systems. 1334-1339 - Alvaro Jover-Alvarez, Alejandro J. Calderón, Iván Rodriguez, Leonidas Kosmidis, Kazi Asifuzzaman, Patrick Uven, Kim Grüttner, Tomaso Poggi, Irune Agirre:
The UP2DATE Baseline Research Platforms. 1340-1343 - Sunghoon Kim, Hyun-jeong Kwon, Eunji Kwon, Youngchang Choi, Tae-Hyun Oh, Seokhyeong Kang:
MDARTS: Multi-objective Differentiable Neural Architecture Search. 1344-1349 - Nhut-Minh Ho, Duy Thanh Nguyen, Himeshi De Silva, John L. Gustafson, Weng-Fai Wong, Ik Joon Chang:
Posit Arithmetic for the Training and Deployment of Generative Adversarial Networks. 1350-1355 - Chuliang Guo, Xingang Yan, Yufei Chen, He Li, Xunzhao Yin, Cheng Zhuo:
Joint Sparsity with Mixed Granularity for Efficient GPU Implementation. 1356-1359 - Karina Vasquez, Yeshwanth Venkatesha, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda:
Activation Density based Mixed-Precision Quantization for Energy Efficient Neural Networks. 1360-1365 - Maximilian Neuner, Inga Abel, Helmut Graeb:
Library-free Structure Recognition for Analog Circuits. 1366-1371 - Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren:
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. 1372-1377 - Muhammad Hassan, Daniel Große, Rolf Drechsler:
System Level Verification of Phase-Locked Loop using Metamorphic Relations. 1378-1381 - Wentian Jin, Shaoyi Peng, Sheldon X.-D. Tan:
Data-Driven Electrostatics Analysis based on Physics-Constrained Deep learning. 1382-1387 - Cheng Tan, Chenhao Xie, Ang Li, Kevin J. Barker, Antonino Tumeo:
AURORA: Automated Refinement of Coarse-Grained Reconfigurable Accelerators. 1388-1393 - Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing:
Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. 1394-1399 - Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Dileep Kurian, Indranil Chakraborty, Sirisha Rani Kale, Nilesh Jain, Tanay Karnik, Ravi R. Iyer, Anuradha Srinivasan:
A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding. 1400-1403 - Madis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein:
Triple Fixed-Point MAC Unit for Deep Learning. 1404-1407 - Jungi Lee, Jongeun Lee:
NP-CGRA: Extending CGRAs for Efficient Processing of Light-weight Deep Neural Networks. 1408-1413 - Cyan Subhra Mishra, Jack Sampson, Mahmut Taylan Kandemir, Vijaykrishnan Narayanan:
Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks. 1414-1419 - Thomas Becnel, Pierre-Emmanuel Gaillardon:
A Deep Learning Approach to Sensor Fusion Inference at the Edge. 1420-1425 - Zichang Liu, Li Chou, Anshumali Shrivastava:
Neighbor Oblivious Learning (NObLe) for Device Localization and Tracking. 1426-1429 - Florenc Demrozi, Fabio Chiarani, Graziano Pravadelli:
A low-cost BLE-based distance estimation, occupancy detection and counting system. 1430-1433 - Meenu Rani Dey, Moumita Patra, Prabhat Mishra:
Real-Time Detection and Localization of Denial-of-Service Attacks in Heterogeneous Vehicular Networks. 1434-1439 - Hwisoo So, Moslem Didehban, Jinhyo Jung, Aviral Shrivastava, Kyoungwoo Lee:
CHITIN: A Comprehensive In-thread Instruction Replication Technique Against Transient Faults. 1440-1445 - Imanol Allende, Nicholas Mc Guire, Jon Pérez, Lisandro Gabriel Monsalve, Javier Fernández, Roman Obermaisser:
Estimation of Linux Kernel Execution Path Uncertainty for Safety Software Test Coverage. 1446-1451 - Benjamin James, Jeffrey Goeders:
Automated Software Compiler Techniques to Provide Fault Tolerance for Real-Time Operating Systems. 1452-1455 - Simone Dutto, Alessandro Savino, Stefano Di Carlo:
Exploring Deep Learning for In-Field Fault Detection in Microprocessors. 1456-1459 - Sami Salamin, Georgios Zervakis, Ourania Spantidi, Iraklis Anagnostopoulos, Jörg Henkel, Hussam Amrouch:
Reliability-Aware Quantization for Anti-Aging NPUs. 1460-1465 - Bert Böddeker, Wilhard von Wendorff, Nam Nguyen, Peter Diehl, Roland Meertens, Rolf Johannson:
Automated driving safety - The art of conscious risk taking - minimum lateral distances to pedestrians. 1466-1471 - Himanshu Agarwal, Rafal Dorociak, Achim Rettberg:
On safety assurance case for deep learning based image classification in highly automated driving. 1472-1477 - Chih-Hong Cheng, Rongjie Yan:
Continuous Safety Verification of Neural Networks. 1478-1483 - Sina Faezi, Rozhin Yasaei, Mohammad Abdullah Al Faruque:
HTnet: Transfer Learning for Golden Chip-Free Hardware Trojan Detection. 1484-1489 - Qazi Arbab Ahmed, Tobias Wiersema, Marco Platzner:
Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. 1490-1495 - Honorio Martín, Elena-Ioana Vatajelu, Giorgio Di Natale:
Identification of Hardware Devices based on Sensors and Switching Activity: a Preliminary Study. 1496-1499 - Turki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi:
Differential Aging Sensor to Detect Recycled ICs using Sub-threshold Leakage Current. 1500-1503 - Rozhin Yasaei, Shih-Yuan Yu, Mohammad Abdullah Al Faruque:
GNN4TJ: Graph Neural Networks for Hardware Trojan Detection at Register Transfer Level. 1504-1509 - Qi Sun, Chen Bai, Hao Geng, Bei Yu:
Deep Neural Network Hardware Deployment Optimization via Advanced Active Learning. 1510-1515 - Yesung Kang, Eunji Kwon, Seunggyu Lee, Younghoon Byun, Youngjoo Lee, Seokhyeong Kang:
Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks. 1516-1521 - Huaipan Jiang, Anup Sarma, Mengran Fan, Jihyun Ryoo, Meenakshi Arunachalam, Sharada Naveen, Mahmut T. Kandemir:
Morphable Convolutional Neural Network for Biomedical Image Segmentation. 1522-1525 - Jongsung Kang, Taewhan Kim:
Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks. 1526-1529 - Shuanglong Liu, Hongxiang Fan, Wayne Luk:
Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA. 1530-1535 - Hisakatsu Yamaguchi, Makiko Ito, Katsuhiro Yoda, Atsushi Ike:
Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management. 1536-1541 - Van-Phu Ha, Olivier Sentieys:
Leveraging Bayesian Optimization to Speed Up Automatic Precision Tuning. 1542-1547 - Ye Wang, Jian Dong, Qian Xu, Gang Qu:
FTApprox: A Fault-Tolerant Approximate Arithmetic Computing Data Format. 1548-1551 - Jorge Echavarria, Stefan Wildermann, Jürgen Teich:
Approximate Logic Synthesis of Very Large Boolean Networks. 1552-1557 - Ravi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile:
Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure. 1558-1563 - Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang:
Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. 1564-1569 - Zhen Zhuang, Xing Huang, Genggeng Liu, Wenzhong Guo, Weikang Qian, Wen-Hao Liu:
ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification. 1570-1573 - Yehuda Kra, Tzachi Noy, Adam Teman:
WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining. 1574-1579 - P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel:
A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. 1580-1585 - Qi Xu, Junpeng Wang, Hao Geng, Song Chen, Xiaoqing Wen:
Reliability-Driven Neuromorphic Computing Systems Design. 1586-1591 - Christopher Münch, Mehdi B. Tahoori:
Testing Resistive Memory based Neuromorphic Architectures using Reference Trimming. 1592-1595 - Arjun Chaudhuri, Jonti Talukdar, Jinwook Jung, Gi-Joon Nam, Krishnendu Chakrabarty:
Fault-Criticality Assessment for AI Accelerators using Graph Convolutional Networks. 1596-1599 - Christian Fibich, Martin Horauer, Roman Obermaisser:
Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs. 1600-1605 - Seyed Mohammad Ali Zeinolabedin, Johannes Partzsch, Christian Mayr:
Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator. 1606-1609 - Hanna Müller, Daniele Palossi, Stefan Mach, Francesco Conti, Luca Benini:
Fünfiiber-Drone: A Modular Open-Platform 18-grams Autonomous Nano-Drone. 1610-1615 - Alex R. Bucknall, Suhaib A. Fahmy:
Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware. 1616-1621 - Rasmus Adler:
Systems Engineering Roadmap for Dependable Autonomous Cyber-Physical Systems. 1622-1625 - Eric Armengaud, Daniel Schneider, Jan Reich, Ioannis Sorokos, Yiannis Papadopoulos, Marc Zeller, Gilbert Regan, Georg Macher, Omar Veledar, Stefan Thalmann, Sohag Kabir:
DDI: A novel technology and innovation model for dependable, collaborative and autonomous systems. 1626-1631 - Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori:
Remote and Stealthy Fault Attacks on Virtualized FPGAs. 1632-1637 - Ilias Giechaskiel, Ken Eguro, Kasper Rasmussen:
Extended Abstract: Covert Channels and Data Exfiltration From FPGAs. 1638 - Shayan Moini, Shanquan Tian, Daniel E. Holcomb, Jakub Szefer, Russell Tessier:
Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs. 1639-1644 - Ognjen Glamocanin, Dina G. Mahmoud, Francesco Regazzoni, Mirjana Stojilovic:
Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks. 1645-1650 - Xiao Moyuan, Tsun-Ming Tseng, Ulf Schlichtmann:
FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs. 1651-1656 - Antonio Franques, Sergi Abadal, Haitham Hassanieh, Josep Torrellas:
Fuzzy-Token: An Adaptive MAC Protocol for Wireless-Enabled Manycores. 1657-1662 - Suraj Paul, Navonil Chatterjee, Prasun Ghosal, Jean-Philippe Diguet:
A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing. 1663-1666 - Aqeeb Iqbal Arka, Janardhan Rao Doppa, Partha Pratim Pande, Biresh Kumar Joardar, Krishnendu Chakrabarty:
ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks. 1667-1672 - Ourania Spantidi, Iraklis Anagnostopoulos, Georgios Fainekos:
Efficient Resource Management of Clustered Multi-Processor Systems Through Formal Property Exploration. 1673-1678 - Sofiane Chetoui, Sherief Reda:
Workload- and User-aware Battery Lifetime Management for Mobile SoCs. 1679-1684 - Mark Sagi, Martin Rapp, Heba Khdr, Yizhe Zhang, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Jörg Henkel, Andreas Herkersdorf:
Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors. 1685-1690 - Anurag Agarwal, Jaspinder Kaur, Shirshendu Das:
Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache. 1691-1696 - Fengkai Yuan, Kai Wang, Rui Hou, Xiaoxin Li, Peinan Li, Lutan Zhao, Jiameng Ying, Amro Awad, Dan Meng:
PiPoMonitor: Mitigating Cross-core Cache Attacks Using the Auto-Cuckoo Filter. 1697-1702 - Prashant Hari Narayan Rajput, Michail Maniatakos:
Towards Non-intrusive Malware Detection for Industrial Control Systems. 1703-1706 - Lei Yu, Linyu Li, Haoyu Wang, Xiaoyu Wang, Houhua He, Xiaorui Gong:
Towards Automated Detection of Higher-Order Memory Corruption Vulnerabilities in Embedded Devices. 1707-1710 - Hassan Nassar, Lars Bauer, Jörg Henkel:
TiVaPRoMi: Time-Varying Probabilistic Row-Hammer Mitigation. 1711-1716 - Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui:
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. 1717-1722 - Yue Shen, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays. 1723-1728 - Weihua Liu, Fei Wu, Jian Zhou, Meng Zhang, Chengmo Yang, Zhonghai Lu, Yu Wang, Changsheng Xie:
Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory. 1729-1732 - Giju Jung, Mohammed E. Fouda, Sugil Lee, Jongeun Lee, Ahmed M. Eltawil, Fadi J. Kurdahi:
Cost- and Dataset-free Stuck-at Fault Mitigation for ReRAM-based Deep Learning Accelerators. 1733-1738 - Tanya Amert, Michael Balszun, Martin Geier, F. Donelson Smith, James H. Anderson, Samarjit Chakraborty:
Timing-Predictable Vision Processing for Autonomous Systems. 1739-1744 - Zhilu Wang, Chao Huang, Yixuan Wang, Clara Hobbs, Samarjit Chakraborty, Qi Zhu:
Bounding Perception Neural Network Uncertainty for Safe Control of Autonomous Systems. 1745-1750 - Sayandip De, Yingkai Huang, Sajid Mohamed, Dip Goswami, Henk Corporaal:
Hardware- and Situation-Aware Sensing for Robust Closed-Loop Control Systems. 1751-1756 - Anirban Ghose, Srijeeta Maity, Arijit Kar, Soumyajit Dey:
Orchestration of Perception Systems for Reliable Performance in Heterogeneous Platforms. 1757-1762 - Yugpratap Singh, Abraham Peedikayil Kuruvila, Kanad Basu:
Hardware-assisted Detection of Malware in Automotive-Based Systems. 1763-1768 - Abhijitt Dhavlle, Sanket Shukla, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao:
HMD-Hardener: Adversarially Robust and Efficient Hardware-Assisted Runtime Malware Detection. 1769-1774 - Zhixin Pan, Jennifer Sheldon, Chamika Sudusinghe, Subodha Charles, Prabhat Mishra:
Hardware-Assisted Malware Detection using Machine Learning. 1775-1780 - Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia:
CASTLE: Architecting Assured System-on-Chip Firmware Integrity. 1781-1786 - Paul Scheffler, Florian Zaruba, Fabian Schuiki, Torsten Hoefler, Luca Benini:
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. 1787-1792 - Wei Mao, Kai Li, Xinang Xie, Shirui Zhao, He Li, Hao Yu:
A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing. 1793-1798 - Chun-Chang Yu, Yu Hen Hu, Yi-Chang Lu, Charlie Chung-Ping Chen:
Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. 1799-1802 - Ahmad M. Radaideh, Paul V. Gratz:
CMRC: Comprehensive Microarchitectural Register Coalescing for GPGPUs. 1803-1808 - Daeyeon Kim, Hyun-jeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo, Seokhyeong Kang:
Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator. 1809-1814 - Tong Qu, Yibo Lin, Zongqing Lu, Yajuan Su, Yayi Wei:
Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing. 1815-1820 - Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu:
Global Placement with Deep Learning-Enabled Explicit Routability Optimization. 1821-1824 - Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar:
MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. 1825-1828 - Aaron C.-W. Liang, Hsuan-Ming Huang, Charles H.-P. Wen:
Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes. 1829-1834 - Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu:
A GPU-enabled Level Set Method for Mask Optimization. 1835-1838 - Ann Franchesca Laguna, Arman Kazemi, Michael T. Niemier, X. Sharon Hu:
In-Memory Computing based Accelerator for Transformer Networks for Long Sequences. 1839-1844 - Mehrshad Zandigohar, Deniz Erdogmus, Gunar Schirner:
NetCut: Real-Time DNN Inference Using Layer Removal. 1845-1850 - Alfio Di Mauro, Moritz Scherer, Jordi Fornt Mas, Basile Bougenot, Michele Magno, Luca Benini:
FlyDVS: An Event-Driven Wireless Ultra-Low Power Visual Sensor Node. 1851-1854 - Sidharth Maheshwari, Rishad A. Shafik, Ian Wilson, Alex Yakovlev, Venkateshwarlu Y. Gudur, Amit Acharyya:
PLEDGER: Embedded Whole Genome Read Mapping using Algorithm-HW Co-design and Memory-aware Implementation. 1855-1858 - Alejandro Hernández-Cano, Yeseong Kim, Mohsen Imani:
A Framework for Efficient and Binary Clustering in High-Dimensional Space. 1859-1864 - Lichuan Luo, He Zhang, Jinyu Bai, Youguang Zhang, Wang Kang, Weisheng Zhao:
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture. 1865-1870 - Yandong Luo, Yuan-Chun Luo, Shimeng Yu:
A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training. 1871-1876 - Hassen Aziza, Said Hamdioui, Moritz Fieback, Mottaqiallah Taouil, Mathieu Moreau:
Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation. 1877-1880 - Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza:
Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. 1881-1886 - Paolo Pazzaglia, Arne Hamann, Dirk Ziegenbein, Martina Maggio:
Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns. 1887-1892 - Debayan Roy, Clara Hobbs, James H. Anderson, Marco Caccamo, Samarjit Chakraborty:
Timing Debugging for Cyber-Physical Systems. 1893-1898 - Wenhong Ma, Guoqi Xie, Renfa Li, Weichen Liu, Hai Helen Li, Wanli Chang:
Efficient AUTOSAR-Compliant CAN-FD Frame Packing with Observed Optimality. 1899-1904 - Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar:
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? 1905-1914 - Falk Rehm, Jörg Seitter, Jan-Peter Larsson, Selma Saidi, Giovanni Stea, Raffaele Zippo, Dirk Ziegenbein, Matteo Andreozzi, Arne Hamann:
The Road towards Predictable Automotive High - Performance Platforms. 1915-1924 - Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, Debjyoti Bhattacharjee, Krishnendu Chakrabarty, Said Hamdioui, Anupam Chattopadhyay, Jens Trommer, Akash Kumar:
Perspectives on Emerging Computation-in-Memory Paradigms. 1925-1934
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