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ORCIDKatsuya Kikuchi
Person information
- affiliation: National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan
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2020 – today
- 2021
[j10]Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata
, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express 18(9): 20210070 (2021)- [j9]Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Analysis and evaluation of noise coupling between through-silicon-vias. IEICE Electron. Express 18(11): 20210139 (2021) - 2020
- [j8]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits 55(10): 2747-2755 (2020)
2010 – 2019
- 2019
- [c20]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs. 3DIC 2019: 1-3 - [c19]Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi:
Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core. 3DIC 2019: 1-4 - [c18]Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC 2019: 1-4 - [c17]Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi:
A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC 2019: 25-28 - 2017
- [j7]Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi:
Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 79: 380-386 (2017) - [c16]Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Katsuya Kikuchi, Masahiro Aoyagi:
Designing Efficient Parallel Processing in 3D Standard-Chip Stacking System with Standard Bus. MCSoC 2017: 128-135 - 2016
- [j6]Wei Feng, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi:
Validation of TSV thermo-mechanical simulation by stress measurement. Microelectron. Reliab. 59: 95-101 (2016) - [j5]Wei Feng, Tung Thanh Bui, Naoya Watanabe, Haruo Shimamoto, Masahiro Aoyagi, Katsuya Kikuchi:
Fabrication and stress analysis of annular-trench-isolated TSV. Microelectron. Reliab. 63: 142-147 (2016) - [j4]Samson Melamed, Naoya Watanabe, Shunsuke Nemoto, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi:
Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits. Microelectron. Reliab. 67: 2-8 (2016) - [c15]Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi, Hidekazu Kikuchi, Azusa Yanagisawa, Akio Nakamura:
Wet cleaning process for high-yield via-last TSV formation. 3DIC 2016: 1-4 - 2015
- [j3]Samson Melamed, Fumito Imura, Hiroshi Nakagawa, Katsuya Kikuchi, Michiya Hagimoto, Yukoh Matsumoto, Masahiro Aoyagi:
Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit. Microelectron. J. 46(12): 1106-1113 (2015) - [c14]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Guard-ring monitoring system for inspecting defects in TSV-based data buses. 3DIC 2015: TS8.18.1-TS8.18.5 - [c13]Samson Melamed, Katsuya Kikuchi, Masahiro Aoyagi:
Investigation of effects of metalization on heat spreading in bump-bonded 3D systems. 3DIC 2015: TS8.30.1-TS8.30.4 - [c12]Tung Thanh Bui, Naoya Watanabe, Masahiro Aoyagi, Katsuya Kikuchi:
Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner. 3DIC 2015: TS8.6.1-TS8.6.4 - 2014
- [c11]Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi:
Substrate monitoring system for inspecting defects in TSV-based data buses. 3DIC 2014: 1-5 - [c10]Wei Feng, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Masahiro Aoyagi:
Analysis of thermal stress distribution for TSV with novel structure. 3DIC 2014: 1-4 - [c9]Katsuya Kikuchi, Masahiro Aoyagi, Masaaki Ujiie, Shinya Takayama:
Ultrawideband ultralow PDN impedance of decoupling capacitor embedded interposers using narrow gap chip parts mounting technology for 3-D integrated LSI system. 3DIC 2014: 1-6 - [c8]Bui Thanh Tung, Xiaojin Cheng, Naoya Watanabe, Fumiki Kato, Katsuya Kikuchi, Masahiro Aoyagi:
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration. 3DIC 2014: 1-4 - 2013
- [c7]Masahiro Aoyagi, Naoya Watanabe, Motohiro Suzuki, Katsuya Kikuchi, Shunsuke Nemoto, Noriaki Arima, Misaki Ishizuka, Koji Suzuki, Toshio Shiomi:
New optical three dimensional structure measurement method of cone shape micro bumps used for 3D LSI chip stacking. 3DIC 2013: 1-5 - [c6]Katsuya Kikuchi, Fumiki Kato, Shunsuke Nemoto, Hiroshi Nakagawa, Masahiro Aoyagi, Youtaro Yasu, Kohji Koshiji:
Investigation of optimized high-density flip-chip interconnect design including micro Au bumps for 3-D stacked LSI packaging. 3DIC 2013: 1-4 - 2011
- [c5]Fumiki Kato, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi:
Hot spots suppression by high thermal conductivity film in thin-sub strate CMOS ICs for 3D integration. 3DIC 2011: 1-4 - [c4]Katsuya Kikuchi, Chihiro Ueda, Fumiaki Fujii, Yutaka Akiyama, Naoya Watanabe, Yasuhiro Kitamura, Toshio Gomyo, Toshikazu Okubo, Tetsuya Koyama, Tadashi Kamada, Masahiro Aoyagi, Kanji Otsuka:
PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system. 3DIC 2011: 1-4 - [c3]Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi:
COOL interconnect low power interconnection technology for scalable 3D LSI design. COOL Chips 2011: 1-3
2000 – 2009
- 2009
- [c2]Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka:
Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. 3DIC 2009: 1-4 - [c1]Koichi Takemura, Katsuya Kikuchi, Chihiro Ueda, Kazuhiro Baba, Masahiro Aoyagi, Kanji Otsuka:
SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. 3DIC 2009: 1-5 - 2008
- [j2]Yasuhiro Yamaji, Tokihiko Yokoshima, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi:
Chemical flip-chip bonding method for fabricating 10-µm-pad-pitch interconnect. IEICE Electron. Express 5(18): 732-737 (2008) - 2006
- [j1]Junso Pak, Masahiro Aoyagi, Katsuya Kikuchi, Joungho Kim:
Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB. IEICE Trans. Electron. 89-C(4): 551-559 (2006)
Coauthor Index
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