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ORCIDKazuya Katsuki
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2000 – 2009
- 2007
[j2]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations. IEICE Trans. Electron. 90-C(4): 699-707 (2007)- [j1]Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. IEICE Trans. Electron. 90-C(10): 1919-1926 (2007) - [c4]Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera:
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. ASP-DAC 2007: 122-123 - 2006
- [c3]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. ASP-DAC 2006: 110-111 - [c2]Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera:
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. FPL 2006: 1-4 - 2005
- [c1]Kazuya Katsuki, Manabu Kotani, Kazutoshi Kobayashi, Hidetoshi Onodera:
A yield and speed enhancement scheme under within-die variations on 90nm LUT array. CICC 2005: 601-604
Coauthor Index
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