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2010 – 2019
- 2013
[j7]Chung-Li Wang, Xiaoheng Chen, Zongwang Li, Shaohua Yang:
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes. IEEE Trans. Commun. 61(1): 24-32 (2013)- 2012
- [j6]Xiaoheng Chen, Shu Lin, Venkatesh Akella:
Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 188-197 (2012) - [j5]Xiaoheng Chen, Chung-Li Wang:
High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2784-2794 (2012) - [c3]Xiaoheng Chen, Chung-Li Wang:
Exploiting the shift property of structured LDPC codes for reduced-complexity sliced message passing based decoder design. ICNC 2012: 471-475 - [i1]Chung-Li Wang, Xiaoheng Chen, Zongwang Li, Shaohua Yang:
A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes. CoRR abs/1207.5555 (2012) - 2011
- [j4]Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella:
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1): 98-111 (2011) - [j3]Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella:
Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(12): 2931-2943 (2011) - [j2]Xiaoheng Chen, Venkatesh Akella:
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. ACM Trans. Reconfigurable Technol. Syst. 4(4): 37:1-37:17 (2011) - 2010
- [j1]Xiaoheng Chen, Shu Lin, Venkatesh Akella:
QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 782-786 (2010)
2000 – 2009
- 2009
- [c2]Xiaoheng Chen, Qin Huang, Shu Lin, Venkatesh Akella:
FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes. Allerton 2009: 600-606 - [c1]Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella:
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. DATE 2009: 1530-1535
Coauthor Index
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