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ORCIDVenkatesh Akella
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- affiliation: University of California, Davis, USA
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2020 – today
- 2024
[c55]Mark Hildebrand, Jason Lowe-Power, Venkatesh Akella:
CachedArrays: Optimizing Data Movement for Heterogeneous Memory Systems. IPDPS 2024: 545-555- [i2]William Shaddix, Mahyar Samani, Marjan Fariborz, S. J. Ben Yoo, Jason Lowe-Power, Venkatesh Akella:
TEGRA - Scaling Up Terascale Graph Processing with Disaggregated Computing. CoRR abs/2404.03155 (2024) - 2023
- [c54]Venkatesh Akella, Marjan Fariborz, Mahyar Samani, S. J. Ben Yoo, Jason Lowe-Power:
Scalable Hardware Acceleration of Graph Processing with Photonic Interconnects. PSC 2023: 1-3 - [c53]Mark Hildebrand
, Jason Lowe-Power, Venkatesh Akella:
Efficient Large Scale DLRM Implementation on Heterogeneous Memory Systems. ISC 2023: 42-61 - 2022
- [j30]Marjan Fariborz, Mahyar Samani, Terry O'Neill, Jason Lowe-Power, S. J. Ben Yoo, Venkatesh Akella:
A Model for Scalable and Balanced Accelerators for Graph Processing. IEEE Comput. Archit. Lett. 21(2): 149-152 (2022) - [c52]Ayaz Akram, Venkatesh Akella, Sean Peisert, Jason Lowe-Power:
SoK: Limitations of Confidential Computing via TEEs for High-Performance Compute Systems. SEED 2022: 121-132 - [c51]Marjan Fariborz, Mahyar Samani, Pouya Fotouhi, Roberto Proietti, Il-Min Yi, Venkatesh Akella, Jason Lowe-Power, Samuel Palermo, S. J. Ben Yoo:
LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads. ISC 2022: 44-64 - 2021
- [c50]Ayaz Akram, Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert:
Performance Analysis of Scientific Computing Workloads on General Purpose TEEs. IPDPS 2021: 1066-1076 - [c49]Mark Hildebrand, Julian T. Angeles, Jason Lowe-Power, Venkatesh Akella:
A Case Against Hardware Managed DRAM Caches for NVRAM Based Systems. ISPASS 2021: 194-204 - [c48]Pouya Fotouhi, Marjan Fariborz, Roberto Proietti, Jason Lowe-Power, Venkatesh Akella, S. J. Ben Yoo:
HTA: A Scalable High-Throughput Accelerator for Irregular HPC Workloads. ISC 2021: 176-194 - 2020
- [j29]Andrew Margenot, Terry O'Neill, Rolf Sommer, Venkatesh Akella:
Predicting soil permanganate oxidizable carbon (POXC) by coupling DRIFT spectroscopy and artificial neural networks (ANN). Comput. Electron. Agric. 168 (2020) - [j28]Maxim Shepovalov, Venkatesh Akella:
FPGA and GPU-based acceleration of ML workloads on Amazon cloud - A case study using gradient boosted decision tree library. Integr. 70: 1-9 (2020) - [c47]Mark Hildebrand, Jawad Khan, Sanjeev Trika, Jason Lowe-Power, Venkatesh Akella:
AutoTM: Automatic Tensor Movement in Heterogeneous Memory Systems using Integer Linear Programming. ASPLOS 2020: 875-890 - [c46]Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems. ICPP 2020: 60:1-60:11 - [i1]Ayaz Akram, Anna Giannakou, Venkatesh Akella, Jason Lowe-Power, Sean Peisert:
Performance Analysis of Scientific Computing Workloads on Trusted Execution Environments. CoRR abs/2010.13216 (2020)
2010 – 2019
- 2019
- [j27]Sree Balaji Girisankar, Mona Nasseri, Jennifer Priscilla, Shu Lin, Venkatesh Akella:
Multiplier-Free Implementation of Galois Field Fourier Transform on a FPGA. IEEE Trans. Circuits Syst. II Express Briefs 66-II(11): 1815-1819 (2019) - 2018
- [c45]Sandeep Rasoori, Venkatesh Akella:
Scalable Hardware Accelerator for Mini-Batch Gradient Descent. ACM Great Lakes Symposium on VLSI 2018: 159-164 - [c44]Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. HiPC 2018: 112-122 - [c43]Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, Christopher J. Nitta:
A case for exposing extra-architectural state in the ISA: position paper. HASP@ISCA 2018: 8:1-8:6 - 2017
- [c42]Paolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo:
Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing Systems. HPCA 2017: 289-300 - [c41]Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. ICCD 2017: 649-652 - 2016
- [c40]Mohammad Motamedi, Philipp Gysel, Venkatesh Akella, Soheil Ghiasi:
Design space exploration of FPGA-based Deep Convolutional Neural Networks. ASP-DAC 2016: 575-580 - [c39]Huan Zhang, Cho-Jui Hsieh, Venkatesh Akella:
HogWild++: A New Mechanism for Decentralized Asynchronous Stochastic Gradient Descent. ICDM 2016: 629-638 - [c38]Paolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo:
Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip. MEMSYS 2016: 377-386 - 2014
- [j26]Frank Maker III, Rajeevan Amirtharajah, Venkatesh Akella:
Runtime Adaptation of Applications Using Design Of Experiments: A Smartphone-Based Case Study. IEEE Embed. Syst. Lett. 6(2): 25-28 (2014) - [j25]Kevin Macdonald, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks. IEEE Trans. Computers 63(3): 650-663 (2014) - [j24]Paul Congdon, Prasant Mohapatra, Matthew K. Farrens, Venkatesh Akella:
Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches. IEEE/ACM Trans. Netw. 22(3): 1007-1020 (2014) - 2013
- [j23]Frank Maker III, Rajeevan Amirtharajah, Venkatesh Akella:
MELOADES: Methodology for long-term online adaptation of embedded software for heterogeneous devices. J. Syst. Archit. 59(8): 643-655 (2013) - [c37]Frank Maker III, Rajeevan Amirtharajah, Venkatesh Akella:
Update rate tradeoffs for improving online power modeling in smartphones. ISLPED 2013: 114-119 - [c36]Roberto Proietti, Christopher J. Nitta, Yawei Yin, Venkatesh Akella, S. J. Ben Yoo:
Scalability and performance of a distributed AWGR-based all-optical token interconnect architecture. OFC/NFOEC 2013: 1-3 - 2012
- [j22]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
DCOF - An Arbitration Free Directly Connected Optical Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 169-182 (2012) - [j21]Xiaohui Ye, S. J. Ben Yoo, Venkatesh Akella:
AWGR-Based Optical Topologies for Scalable and Efficient Global Communications in Large-Scale Multi-Processor Systems. JOCN 4(9): 651-662 (2012) - [j20]Xiaoheng Chen, Shu Lin, Venkatesh Akella:
Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 188-197 (2012) - [c35]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing. IPDPS 2012: 1144-1155 - 2011
- [j19]Xiaohui Ye, Roberto Proietti, Yawei Yin, S. J. Ben Yoo, Venkatesh Akella:
Buffering and Flow Control in Optical Switches for High Performance Computing. JOCN 3(8): A59-A72 (2011) - [j18]Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella:
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1): 98-111 (2011) - [j17]Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella:
Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(12): 2931-2943 (2011) - [j16]Xiaoheng Chen, Venkatesh Akella:
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. ACM Trans. Reconfigurable Technol. Syst. 4(4): 37:1-37:17 (2011) - [c34]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Addressing system-level trimming issues in on-chip nanophotonic networks. HPCA 2011: 122-131 - [c33]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Resilient microring resonator based photonic networks. MICRO 2011: 95-104 - [c32]Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella:
Inferring packet dependencies to improve trace based simulation of on-chip networks. NOCS 2011: 153-160 - 2010
- [j15]Eric Jung, Frank Maker III, Tang Lung Cheung, Xin Liu, Venkatesh Akella:
Markov decision process (MDP) framework for software power optimization using call profiles on mobile phones. Des. Autom. Embed. Syst. 14(1): 131-159 (2010) - [j14]Haijun Yang, Zhong Pan, Venkatesh Akella, Chen-Nee Chuah, S. J. Ben Yoo:
Optical Router Control Architecture and Contention Resolution Algorithms Capable of Asynchronous, Variable-Length Packet Switching. JOCN 2(9): 745-759 (2010) - [j13]Xiaoheng Chen, Shu Lin, Venkatesh Akella:
QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 782-786 (2010) - [c31]Xiaohui Ye, Yawei Yin, S. J. Ben Yoo, Paul Vincent Mejia, Roberto Proietti, Venkatesh Akella:
DOS: a scalable optical switch for datacenters. ANCS 2010: 24 - [c30]Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
Performance Evaluation of a Multicore System with Optically Connected Memory Modules. NOCS 2010: 215-222
2000 – 2009
- 2009
- [c29]Xiaoheng Chen, Qin Huang, Shu Lin, Venkatesh Akella:
FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes. Allerton 2009: 600-606 - [c28]Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella:
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. DATE 2009: 1530-1535 - [c27]Tang Lung Cheung, Kari Okamoto, Frank Maker III, Xin Liu, Venkatesh Akella:
Markov decision process (MDP) framework for optimizing software on mobile phones. EMSOFT 2009: 11-20 - 2008
- [c26]John Y. Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Frederic T. Chong:
Credit-based dynamic reliability management using online wearout detection. Conf. Computing Frontiers 2008: 139-148 - [c25]Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella:
OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. Hot Interconnects 2008: 57-63 - [c24]Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
Design and evaluation of an optical CPU-DRAM interconnect. ICCD 2008: 492-497 - 2007
- [j12]John Y. Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Roland Geyer, Frederic T. Chong:
Life Cycle Aware Computing: Reusing Silicon Technology. Computer 40(12): 56-61 (2007) - [j11]John Y. Oliver, Diana Franklin, Frederic T. Chong, Venkatesh Akella:
Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture. Trans. High Perform. Embed. Archit. Compil. 1: 259-278 (2007) - 2006
- [j10]John Y. Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella:
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications. J. Embed. Comput. 2(2): 157-166 (2006) - [c23]John Y. Oliver, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, Venkatesh Akella:
Tile size selection for low-power tile-based architectures. Conf. Computing Frontiers 2006: 83-94 - [c22]Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella:
Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. HiPC 2006: 123-134 - 2005
- [c21]Gouri Landge, Mihaela van der Schaar, Venkatesh Akella:
Generic modeling of complexity for motion-compensated wavelet video decoders. Electronic Imaging: Image and Video Communications and Processing 2005 - [c20]Gouri Landge, Mihaela van der Schaar, Venkatesh Akella:
Complexity metric driven energy optimization framework for implementing MPEG-21 scalable video decoders. ICASSP (2) 2005: 1141-1144 - [c19]Haijun Yang, Venkatesh Akella, Chen-Nee Chuah, S. J. Ben Yoo:
Scheduling optical packets in wavelength, time, and space domains for all-optical packet switching routers. ICC 2005: 1836-1842 - [c18]Venkatesh Akella, Mihaela van der Schaar, Wen-Fu Kao:
Proactive Energy Optimization Algorithms for Wavelet-Based Video Codecs on Power-Aware Processors. ICME 2005: 566-569 - 2004
- [c17]Mihaela van der Schaar, Deepak S. Turaga, Venkatesh Akella:
Rate-distortion-complexity adaptive video compression and streaming. ICIP 2004: 2051-2054 - [c16]John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong:
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ISCA 2004: 150-161 - [c15]John Y. Oliver, Venkatesh Akella, Frederic T. Chong:
Efficient orchestration of sub-word parallelism in media processors. SPAA 2004: 225-234 - 2003
- [j9]S. J. Ben Yoo, Fei Xue, Yash Bansal, Julie Taylor, Zhong Pan, Jing Cao, Min-Yong Jeon, Tony Nady, Gary Goncher, Kirk Boyer, Kari Okamoto, Shin Kamei, Venkatesh Akella:
High-performance optical-label switching packet routers and smart edge routers for the next-generation Internet. IEEE J. Sel. Areas Commun. 21(7): 1041-1051 (2003) - [c14]John Y. Oliver, Venkatesh Akella:
Improving DSP Performance with a Small Amount of Field Programmable Logic. FPL 2003: 520-532 - [c13]John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong:
Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. PACS 2003: 73-85 - 2001
- [c12]Tony Werner, Venkatesh Akella:
An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. ASYNC 2001: 140-151
1990 – 1999
- 1999
- [c11]Nithya Raghavan, Venkatesh Akella, Smita Bakshi:
Automatic Insertion of Gated Clocks at Register Transfer Level. VLSI Design 1999: 48-54 - 1998
- [j8]Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo:
Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. IEEE Trans. Computers 47(7): 802-811 (1998) - [j7]Dave Johnson, Venkatesh Akella, Bret Stott:
Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 731-740 (1998) - 1997
- [j6]Tony Werner, Venkatesh Akella:
Asynchronous Processor Survey. Computer 30(11): 67-76 (1997) - 1996
- [c10]Tony Werner, Venkatesh Akella:
Counterflow pipeline based dynamic instruction scheduling. ASYNC 1996: 69-79 - [c9]Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo:
Limitations of VLSI Implementation of Delay-Insensitive Codes. FTCS 1996: 208-217 - 1995
- [c8]Bret Stott, Dave Johnson, Venkatesh Akella:
Asynchronous 2-D discrete cosine transform core processor. ICCD 1995: 380-385 - 1994
- [j5]Venkatesh Akella, Ganesh Gopalakrishnan:
CFSIM: A Concurrent Compiled Code Functional Simulator for hopCP. Int. J. Comput. Simul. 4(4): 375-394 (1994) - [j4]Venkatesh Akella, Ganesh Gopalakrishnan:
Specification and Validation of Control-Intensive IC's in hopCP. IEEE Trans. Software Eng. 20(6): 405-423 (1994) - [j3]Ganesh Gopalakrishnan, Venkatesh Akella:
High-level optimizations in compiling process descriptions to asynchronous circuits. J. VLSI Signal Process. 7(1-2): 33-45 (1994) - [c7]Prabhakar Kudva, Venkatesh Akella:
A technique for estimating power in asynchronous circuits. ASYNC 1994: 166-175 - [c6]Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella:
Performance Analysis and Optimization of Asynchronous Circuits. ICCD 1994: 221-224 - [c5]Prabhakar Kudva, Venkatesh Akella:
Testing two-phase transition signaling based self-timed circuits in a synthesis environment. HLSS 1994: 104-111 - 1993
- [c4]Ganesh Gopalakrishnan, Venkatesh Akella:
A transformational approach to asynchronous high-level synthesis. VLSI 1993: 201-210 - 1992
- [j2]Ganesh Gopalakrishnan, Venkatesh Akella:
VLSI asynchronous systems: specification and synthesis. Microprocess. Microsystems 16(10): 517-527 (1992) - [c3]Venkatesh Akella, Ganesh Gopalakrishnan:
SHILPA: a high-level synthesis system for self-timed circuits. ICCAD 1992: 587-591 - [c2]Venkatesh Akella, Ganesh Gopalakrishnan:
From Process-Oriented Functional Specifications to Efficient Asynchronous Circuits. VLSI Design 1992: 324-325
1980 – 1989
- 1989
- [j1]Ganesh Gopalakrishnan, Richard M. Fujimoto, Venkatesh Akella, Narayana Mani:
HOP: A process model for synchronous hardware; semantics and experiments in process composition. Integr. 8(3): 209-247 (1989) - [c1]Ganesh Gopalakrishnan, Narayana Mani, Venkatesh Akella:
Parallel Composition of Lockstep Synchronous Processes for Hardware Validation: Divide-and-Conquer Composition. Automatic Verification Methods for Finite State Systems 1989: 374-382
Coauthor Index
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