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ORCIDToshihiro Katashita
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2020 – today
- 2024
[j11]Hiroshi Fuketa
, Toshihiro Katashita, Yohei Hori, Masakazu Hioki:
Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation. IEEE Access 12: 102470-102480 (2024)- [c14]Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino:
FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. ACNS Workshops (1) 2024: 65-83 - 2021
- [j10]Yusuke Yano, Kengo Iokibe, Toshiaki Teshima, Yoshitaka Toyota, Toshihiro Katashita, Yohei Hori:
Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices. IEICE Trans. Commun. 104-B(2): 178-186 (2021) - 2020
- [j9]Yasuhiro Ogasahara, Yohei Hori, Toshihiro Katashita, Tomoki Iizuka, Hiromitsu Awano, Makoto Ikeda, Hanpei Koike:
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. Integr. 71: 144-153 (2020)
2010 – 2019
- 2019
- [c13]Risa Yashiro, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama:
A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme. SECITC 2019: 78-94 - 2018
- [j8]Toshihiro Katashita, Masakazu Hioki, Yohei Hori, Hanpei Koike:
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. IEICE Trans. Inf. Syst. 101-D(2): 303-313 (2018) - 2017
- [c12]Toshihiro Katashita, Yohei Hori, Yasuhiro Ogasahara:
Prototype of USB stick-sized PUF module for authentication and key generation. GCCE 2017: 1-2 - 2015
- [j7]Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki:
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1429-1438 (2015) - 2014
- [j6]Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger:
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. 97-C(4): 272-279 (2014) - [j5]Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara:
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. J. Inf. Process. 22(2): 344-356 (2014) - 2013
- [j4]Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh:
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. IEICE Trans. Inf. Syst. 96-D(11): 2333-2343 (2013) - [j3]Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata:
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2533-2541 (2013) - [c11]Toshihiro Katashita, Akihiko Sasaki, Yohei Hori:
A novel smart card development platform for evaluating physical attacks and PUFs. GCCE 2013: 37-39 - [c10]Yohei Hori, Toshihiro Katashita, Kazukuni Kobara:
Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA. GCCE 2013: 217-218 - 2012
- [j2]Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki:
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 827-840 (2012) - [c9]Takeshi Sugawara, Daisuke Suzuki, Toshihiro Katashita:
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI. FDTC 2012: 16-23 - 2011
- [c8]Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh:
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST 2011: 87-92 - [c7]Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh:
Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. ReConFig 2011: 223-228 - 2010
- [c6]Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
Hardware Implementations of Hash Function Luffa. HOST 2010: 130-134 - [c5]Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh:
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. ReConFig 2010: 298-303
2000 – 2009
- 2009
- [c4]Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
Development of side-channel attack standard evaluation environment. ECCTD 2009: 403-408 - 2008
- [c3]Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
Enhanced Correlation Power Analysis Using Key Screening Technique. ReConFig 2008: 403-408 - 2007
- [j1]Toshihiro Katashita, Yoshinori Yamaguchi, Atusi Maeda, Kenji Toda:
FPGA-Based Intrusion Detection System for 10 Gigabit Ethernet. IEICE Trans. Inf. Syst. 90-D(12): 1923-1931 (2007) - 2006
- [c2]Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi:
Highly Efficient String Matching Circuit for IDS with FPGA. FCCM 2006: 285-286 - [c1]Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi:
A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection. FPL 2006: 1-4
Coauthor Index
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